A semiconductor portion of a semiconductor device includes a semiconductor layer with a drift zone of a first conductivity type and at least one impurity zone of a second, opposite conductivity type. The impurity zone adjoins a first surface of the semiconductor portion in an element area. A connection layer directly adjoins the semiconductor layer opposite to the first surface. At a distance to the first surface an overcompensation zone is formed in an edge area that surrounds the element area. The overcompensation zone and the connection layer have opposite conductivity types. In a direction vertical to the first surface, a portion of the drift zone is arranged between the first surface and the overcompensation zone. In case of locally high current densities, the overcompensation zone injects charge carriers into the semiconductor layer that locally counter a further increase of electric field strength and reduce the risk of avalanche breakdown.

A semiconductor device includes a semiconductor substrate and a p-doped layer formed on the substrate having a dislocation density exceeding 10.sup.8 cm.sup.2. An n-type layer is formed on or in the p-doped layer. The n-type layer includes a II-VI material configured to tolerate the dislocation density to form an electronic device with reduced leakage current over a device with a III-V n-type layer.

Junction diodes fabricated in standard CMOS logic processes can be used as program selectors with at least one heat sink or heater to assist programming for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The heat sink can be at least one thin oxide area, extended OTP element area, or other conductors coupled to the OTP element to assist programming. A heater can be at least one high resistance area such as an unsilicided polysilicon, unsilicided active region, contact, via, or combined in serial, or interconnect to generate heat to assist programming. The OTP device has at least one OTP element coupled to at least one diode in a memory cell. The diode can be constructed by P+ and N+ active regions in a CMOS N well, or on an isolated active region as the P and N terminals of the diode. The isolation between P+ and the N+ active regions of the diode in a cell or between cells can be provided by dummy MOS gate, SBL, or STI/LOCOS isolations. The OTP element can be polysilicon, silicided polysilicon, silicide, polymetal, metal, metal alloy, local interconnect, metal-0, thermally isolated active region, CMOS gate, or combination thereof.

A semiconductor device is disclosed. In a surface layer of a front surface of an n-type semiconductor substrate, an anode layer is provided in an element activation portion and an annular p-type guard ring and an n-type high-concentration surface region are provided in an annular termination breakdown voltage region which surrounds the outer circumference of the anode layer. The impurity concentration of the n-type high-concentration surface region is higher than that of the semiconductor substrate and is lower than that of the p-type guard ring. The depth of the n-type high-concentration surface region is less than that of the guard ring. The anode layer and the guard ring are formed while the oxygen concentration of the semiconductor substrate is set to be equal to or more than 110.sup.16/cm.sup.3 and equal to or less than 110.sup.18/cm.sup.3.

A semiconductor device includes: a silicon substrate that includes a high-concentration layer containing first conductivity type impurities; a low-concentration layer formed on the high-concentration layer and containing first conductivity type impurities; a first electrode and a second electrode formed on the low-concentration layer; a vertical semiconductor element that allows current to flow between the second electrode and the high-concentration layer; and a first trench unit that realizes electric connection between the first electrode and the high-concentration layer. The first trench unit consists of first polysilicon containing first conductivity type impurities, and a diffusion layer configured to surround the first polysilicon in a plan view and to contain first conductivity type impurities. The first polysilicon is configured to reach the high-concentration layer by penetrating the low-concentration layer. Respective concentrations of the first conductivity type impurities contained in the first polysilicon and in the diffusion layer are kept constant in a direction from the low-concentration layer to the high-concentration layer.

A MOSFET device and fabrication method are disclosed. The MOSFET has a drain in chip plane with an epitaxial layer overlay atop. The MOSFET further comprises: a Kelvin-contact body and an embedded Kelvin-contact source; a trench gate extending into the epitaxial layer; a lower contact trench extending through the Kelvin-contact source and at least part of the Kelvin-contact body defining respectively a vertical source-contact surface and a vertical body-contact surface; a patterned dielectric layer atop the Kelvin-contact source and the trench gate; a patterned top metal layer. As a result: a planar ledge is formed atop the Kelvin-contact source; the MOSFET device exhibits a lowered body Kelvin contact impedance and, owing to the presence of the planar ledge, a source Kelvin contact impedance that is lower than an otherwise MOSFET device without the planar ledge; and an integral parallel Schottky diode is also formed.

The invention provides a semiconductor device. The semiconductor device includes a buried oxide layer disposed on a substrate. A semiconductor layer having a first conduction type is disposed on the buried oxide layer. A first well doped region having a second conduction type is disposed in the semiconductor layer. A cathode doped region having the second conduction type is disposed in the first well doped region. A first anode doped region having the first conduction type is disposed in the first well doped region, separated from the cathode doped region. A first distance from a bottom boundary of the first anode doped region to a top surface of the semiconductor layer is greater than a second distance from the bottom boundary to an interface between the semiconductor layer and the buried oxide layer.

A semiconductor structure includes a substrate; and a buffer layer and a heterojunction structure layer which are disposed on the substrate sequentially, along a direction perpendicular to a direction from the substrate to the buffer layer, the buffer layer includes a plurality of ion implanted regions disposed at intervals, and the plurality of ion implanted regions include an impurity ion. The impurity ion is implanted into the buffer layer at intervals, so that different threshold voltages are formed at the heterojunction structure layer located at different positions in the buffer layer, which makes devices open gradually in a width direction of channels, to relieve decrease of a trans-conductance curve at a relatively large drain current, improving trans-conductance flatness of the devices, and further improving linearity of the devices.

In one aspect, a diode comprises: a semiconductor layer having a first side and a second side opposite the first side, the semiconductor layer having a thickness between the first side and the second side, the thickness of the semiconductor layer being based on a mean free path of a charge carrier emitted into the semiconductor layer; a first metal layer deposited on the first side of the semiconductor layer; and a second metal layer deposited on the second side of the semiconductor layer.

An ESD (electrostatic discharge) protection device includes a first III-nitride p-i-n diode and a second III-nitride p-i-n diode connected to the first III-nitride p-i-n diode in an antiparallel arrangement configured to provide voltage clamping at 5V or less under forward bias of either the first or second III-nitride p-i-n diode for transient current in both forward and reverse directions. A corresponding method of manufacturing the ESD protection device is also provided.