A diode includes a semiconductor substrate having a surface; a first contact region disposed at the surface of the semiconductor substrate and having a first conductivity type; and a second contact region disposed at the surface, laterally spaced from the first contact region, and having a second conductivity type. The diode also includes a buried region disposed in the semiconductor substrate vertically adjacent to the first contact region, having the second conductivity type, and electrically connected with the second contact region; and an isolation region disposed at the surface between the first and second contact regions. The diode also includes a separation region disposed at the surface between the first contact region and the isolation region, the separation region formed from a portion of a first well region disposed in the semiconductor substrate that extends to the surface.

A planar diode and method of making the same employing only one mask. The diode is formed by coating a substrate with an oxide, removing a central portion of the oxide to define a window through which dopants are diffused. The substrate is given a Ni/Au plating to provide ohmic contact surfaces, and the oxide on the periphery of the window is coated with a polyimide passivating agent overlying the P/N junction.

A semiconductor device may include a diode pattern including a first conductive region and a second conductive region having opposite conductivity types to each other on a base insulating layer, an insulating layer covering the diode pattern on the base insulating layer, a wiring portion on the insulating layer; and a through connector extending through the insulating layer at a periphery of the diode pattern to electrically connect the diode pattern and the wiring portion.

A p-type semiconductor region formed in a front surface side of the semiconductor substrate. An n-type field stop (FS) region including protons as a donor is formed in a rear surface side of the semiconductor substrate. A concentration distribution of the donor in the FS region includes a first, second, third and fourth peaks in order from a front surface to the rear surface. A maximum point of peak concentration of the second peak is lower than a maximum point of peak concentration of the first peak.

Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a well region disposed within a semiconductor substrate and comprises a first doping type. A gate electrode overlies the well region. A first contact region is disposed within the well region and comprises a second doping type opposite the first doping type. A second contact region is disposed within the semiconductor substrate and laterally offset from the well region. The second contact region comprises the first doping type and the gate electrode is disposed between the first contact region and the second contact region. A gate dielectric layer is disposed between the semiconductor substrate and the gate electrode, where a thickness of the gate dielectric layer is greater than about 140 Angstroms.

A semiconductor chip of a TVS diode includes a first surface and a second surface at aside opposite the first surface. The semiconductor chip includes first and second pin junctions fora first polarity direction, and a diode-paired region. The diode-paired region includes a high-concentration region of a first conductance type, first and second low-concentration regions that have a lower impurity concentration than the high-concentration region, an isolation region isolating the first and second low-concentration regions, first and second contact regions of a second conductance type, and an internal region of the second conductance type contacting the high-concentration region and arranged closer to the second surface than the high-concentration region. The internal region is arranged overlapping both the first and second low-concentration regions in plan view.

A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a gate electrode, a first source electrode, a second source electrode, and a drain electrode. The second nitride-based semiconductor layer includes a drift region doped, a first barrier region, and a second barrier region. The first and second barrier regions extend downward from a top surface of the second nitride-based semiconductor layer and are separated from each other by a portion of the drift region. The gate electrode is disposed on the first barrier region. The first source electrode is disposed on the portion of the drift region. The second source electrode is disposed on the second barrier region and is electrically coupled with the first source electrode. The drain electrode is connected to the first nitride-based semiconductor layer.

Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a well region disposed within a semiconductor substrate and having a first doping type. A gate electrode overlies the well region. A first contact region is disposed within the well region and comprises a second doping type opposite the first doping type. A second contact region is disposed within the semiconductor substrate and is laterally offset from the well region. The second contact region comprises the first doping type and the gate electrode is disposed between the first contact region and the second contact region. A gate dielectric layer is disposed between the semiconductor substrate and the gate electrode.

In a power semiconductor device, the present disclosure is intended to control tradeoff characteristics while realizing operation in a high-speed side range of the tradeoff characteristics without depending on a carrier lifetime control technique. An n+ cathode layer includes a first n+ cathode layer contacting a second metal layer, and a second n+ cathode layer provided between the first n+ cathode layer and an n buffer layer while contacting the first n+ cathode layer and the n buffer layer. Crystal defect density in the first n+ cathode layer is higher than crystal defect density in the second n+ cathode layer. The n+ cathode layer is absent in an intermediate region and a terminal region.

A stacked high-blocking III-V semiconductor power diode and manufacturing method, wherein the III-V semiconductor power diode comprises a first highly doped semiconductor contact area, a low-doped semiconductor drift region disposed beneath the first semiconductor contact area, a highly doped second semiconductor contact area disposed beneath the semiconductor drift region, and two terminal contact layers, at least the first semiconductor contact area forms a core stack, the core stack is surrounded by a dielectric frame region along the side face, the upper surface or lower surface of the core stack and the dielectric frame region terminate with each other or form a step with respect to each other, and semiconductor areas of the III-V semiconductor power diode arranged beneath the first semiconductor contact area are each either surrounded by the core stack or form a carrier portion.