A capacitor structure is described. A capacitor structure including a substrate; a source/drain region formed in the substrate to form an active area having an active area width; and a plurality of gates formed above the substrate. The source/drain region having a reflection symmetry. Each of the plurality of gates having a gate width. The gate width is configured to be less than said active area width. And, the plurality of gates are formed to have reflection symmetry.

Described herein are switches with asymmetrical anti-series varactor pairs to improve switching performance. The disclosed switches can include asymmetrical varactor pairs to reduce distortions. The asymmetry in the varactor pairs can be associated with geometry of each varactor in the pair. The disclosed switches can stack both symmetrical and asymmetrical varactor pairs. The disclosed switches with asymmetrical anti-series varactor pairs can be configured to improve both H2 and H3 simultaneously.

Macro-transistor structures are disclosed. In some cases, the macro-transistor structures have the same number of terminals and properties similar to long-channel transistors, but are suitable for analog circuits in deep-submicron technologies at deep-submicron process nodes. The macro-transistor structures can be implemented, for instance, with a plurality of transistors constructed and arranged in series, and with their gates tied together, generally referred to herein as a transistor stack. One or more of the serial transistors within the stack can be implemented with a plurality of parallel transistors and/or can have a threshold voltage that is different from the threshold voltages of other transistors in the stack. Alternatively, or in addition, one or more of the serial transistors within the macro-transistor can be statically or dynamically controlled to tune the performance characteristics of the macro-transistor. The macro-transistor can be used in numerous circuits, such as varactors, VCOs, PLLs, and tunable circuits.

A capacitance diode or variable capacitance diode includes first and second electrodes and a layer configuration disposed in contact-making fashion between the two electrodes. The layer configuration has, one after the other in a direction from the first electrode towards the second electrode, a layer formed of a ferroelectric material and an electrically insulating layer formed of a dielectric material having electrically charged defects. A method for producing a capacitance diode or a variable capacitance diode, a storage device and a detector including a capacitance diode or a variable capacitance diode are also provided.

A level shift driver circuit comprises a level shift circuit and a driver circuit. The driver circuit comprises a first and a second P-type transistors and a first and a second N-type transistors coupled in series. When a first input signal of the level shift circuit is at an operative voltage, the level shift circuit turns off the second N-type transistor. A control terminal of the first N-type transistor receives the operative voltage to avoid a gate-induced drain leakage current of the second N-type transistor. When the first input signal is at a system base voltage, the level shift circuit turns off the first P-type transistor. A control terminal of the second P-type transistor receives the operative voltage to avoid a gate-induced drain leakage current of the first P-type transistor.

Implementations described herein provide a chucking circuit for a pixilated electrostatic chuck which enables both lateral and azimuthal tuning of the RF coupling between an electrostatic chuck and a substrate placed thereon. In one embodiment, a chucking circuit for an electrostatic chuck (ESC) has one or more chucking electrodes disposed in a dielectric body of the ESC, a plurality of pixel electrodes disposed in the dielectric body, and a chucking circuit having the one or more chucking electrodes and the plurality of pixel electrodes, the chucking circuit operable to electrostatically chuck a substrate to a workpiece support surface of the ESC, the chucking circuit having a plurality of secondary circuits, wherein each secondary circuit includes at least one capacitor of a plurality of capacitors, each secondary circuit is configured to independently control an impedance between one of the pixel electrodes and a ground.

Implementations described herein provide a chucking circuit for a pixilated electrostatic chuck which enables both lateral and azimuthal tuning of the RF coupling between an electrostatic chuck and a substrate placed thereon. In one embodiment, a chucking circuit for an electrostatic chuck (ESC) has one or more chucking electrodes disposed in a dielectric body of the ESC, a plurality of pixel electrodes disposed in the dielectric body, and a chucking circuit having the one or more chucking electrodes and the plurality of pixel electrodes, the chucking circuit operable to electrostatically chuck a substrate to a workpiece support surface of the ESC, the chucking circuit having a plurality of secondary circuits, wherein each secondary circuit includes at least one capacitor of a plurality of capacitors, each secondary circuit is configured to independently control an impedance between one of the pixel electrodes and a ground.

The invention provides a layout pattern of a semiconductor varactor, which comprises a plurality of varactor units arranged on a substrate, wherein each varactor unit comprises a plurality of fin structures arranged in parallel with each other, a plurality of gate structures arranged in parallel with each other, located on the substrate and spanning the fin structures, and a gate metal layer electrically connected with the plurality of gate structures.

The invention provides a layout pattern of a semiconductor varactor, which comprises a plurality of varactor units arranged on a substrate, wherein each varactor unit comprises a plurality of fin structures arranged in parallel with each other, a plurality of gate structures arranged in parallel with each other, located on the substrate and spanning the fin structures, and a gate metal layer electrically connected with the plurality of gate structures.

A packaged integrated circuit device includes a die that includes integrated radio frequency (RF) circuitry. The packaged integrated circuit device also includes a package substrate including metal layers electrically connected to the RF circuitry. The packaged integrated circuit device further includes an impedance adapter electrically connected to the RF circuitry and disposed between the die and the package substrate. The impedance adapter includes a passive component disposed on or in a body of the impedance adapter.