The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device comprises a substrate, a first gate electrode, a second gate electrode, a first doped region, a second doped region, a third doped region, and a first interconnection structure. The substrate comprises a well region of a first conductive type. The first and second gate electrodes are disposed on the substrate. The first, second, and third doped regions are embedded within the well region and are of the first conductive type. The first interconnection structure electrically connects the first gate electrode and the second gate electrode. The first doped region and the second doped region are disposed on opposite sides of the first gate electrode.

The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device comprises a substrate, a first gate electrode, a second gate electrode, a first doped region, a second doped region, a third doped region, and a first interconnection structure. The substrate comprises a well region of a first conductive type. The first and second gate electrodes are disposed on the substrate. The first, second, and third doped regions are embedded within the well region and are of the first conductive type. The first interconnection structure electrically connects the first gate electrode and the second gate electrode. The first doped region and the second doped region are disposed on opposite sides of the first gate electrode.

Various embodiments of the present disclosure are directed towards an integrated chip including a first doped region in a substrate and comprising a first doping type. A gate structure is over the first doped region. A pair of contact regions are in the substrate on opposing sides of the gate structure and comprising the first doping type. The first doped region continuously laterally extends between the pair of contact regions and contacts the pair of contact regions. A second doped region is in the substrate and along a bottom of the first doped region. The second doped region comprises a second doping type opposite the first doping type.

Various embodiments of the present disclosure are directed towards an integrated chip including a first doped region in a substrate and comprising a first doping type. A gate structure is over the first doped region. A pair of contact regions are in the substrate on opposing sides of the gate structure and comprising the first doping type. The first doped region continuously laterally extends between the pair of contact regions and contacts the pair of contact regions. A second doped region is in the substrate and along a bottom of the first doped region. The second doped region comprises a second doping type opposite the first doping type.

A varactor structure including a substrate, a first conductive layer, a second conductive layer, a first dielectric layer, a second dielectric layer, a first doped region, and a second doped region is provided. The first conductive layer is located on the 5 substrate. The second conductive layer is located on the first conductive layer. The first dielectric layer is located between the substrate and the first conductive layer. The second dielectric layer is located between the first conductive layer and the second conductive layer. The first doped region and the second doped region are located in the substrate at two sides of the first conductive layer. The second conductive layer is 10 electrically connected to the first doped region and the second doped region.

An electronic device is provided. The electronic device includes a bonding point, an electrostatic discharge protection circuit and a scan transistor. The electrostatic discharge protection circuit is electrically connected to the bonding point. The scan transistor has a first terminal, a second terminal and a control terminal. The second terminal of the scan transistor is electrically connected to the bonding point and the electrostatic discharge protection circuit.

An electronic device is provided. The electronic device includes a bonding point, an electrostatic discharge protection circuit and a scan transistor. The electrostatic discharge protection circuit is electrically connected to the bonding point. The scan transistor has a first terminal, a second terminal and a control terminal. The second terminal of the scan transistor is electrically connected to the bonding point and the electrostatic discharge protection circuit.

Embodiments herein relate to systems and methods for utilizing hysteresis as a mechanism of analysis of a sample. A system for analyzing a fluid sample is included having a controller circuit and a chemical sensor element. The chemical sensor element can include one or more discrete binding detectors that can include one or more graphene varactors. The system can include measurement circuitry having an electrical voltage generator configured to generate an applied voltage at a plurality of voltage values to be applied to the one or more graphene varactors. The system can include a measurement circuit having a capacitance sensor configured to measure capacitance of the discrete binding detectors resulting from the applied voltage. The system for analyzing the fluid sample can be configured to measure hysteresis effects related to capacitance versus voltage values obtained from the one or more graphene varactors. Other embodiments are also included herein.

Embodiments herein relate to systems and methods for utilizing hysteresis as a mechanism of analysis of a sample. A system for analyzing a fluid sample is included having a controller circuit and a chemical sensor element. The chemical sensor element can include one or more discrete binding detectors that can include one or more graphene varactors. The system can include measurement circuitry having an electrical voltage generator configured to generate an applied voltage at a plurality of voltage values to be applied to the one or more graphene varactors. The system can include a measurement circuit having a capacitance sensor configured to measure capacitance of the discrete binding detectors resulting from the applied voltage. The system for analyzing the fluid sample can be configured to measure hysteresis effects related to capacitance versus voltage values obtained from the one or more graphene varactors. Other embodiments are also included herein.

Various embodiments of the present disclosure are directed towards an integrated chip including a well region in a substrate and comprising a first dopant type. A dielectric layer is over the well region. A conductive structure is over the dielectric layer. A first doped region and a second doped region are in the substrate and comprise the first dopant type. The conductive structure is spaced laterally between the first and second doped regions. A depletion enhancement region is in the substrate and is below the well region. The depletion enhancement region comprises a second dopant type different from the first dopant type and buts a bottom of the well region.