In examples, a power device comprises a first wide bandgap semiconductor die including a high-side transistor; a second wide bandgap semiconductor die including a low-side transistor; and a conductive device coupled to the first and second wide bandgap semiconductor dies. The conductive device comprises a first layer including a first metal member having fingers at first and second ends of the first metal member, a second metal member having fingers interleaved with fingers of the first metal member at the first end, and a third metal member having fingers interleaved with fingers of the first metal member at the second end. The conductive device also comprises multiple layers in vertical alignment with the first layer, the first, second, and third metal members extending through the multiple layers. The conductive device also comprises a dielectric material covering the first layer and the multiple layers. The power device comprises a connection layer coupling the conductive device to each of the first and second wide bandgap semiconductor dies, with the connection layer including the first, second, and third metal members, and with the first metal member having connection layer fingers at the first and second ends of the first metal member. The second metal member has connection layer fingers interleaved with connection layer fingers of the first metal member at the first end, and the third metal member has connection layer fingers interleaved with connection layer fingers of the first metal member at the second end.

A lateral III-N device has a vertical gate module with III-N material orientated in an N-polar or a group-III polar orientation. A III-N material structure has a III-N buffer layer, a III-N barrier layer, and a III-N channel layer. A compositional difference between the III-N barrier layer and the III-N channel layer causes a 2DEG channel to be induced in the III-N channel layer. A p-type III-N body layer is disposed over the III-N channel layer in a source side access region but not over a drain side access region. A n-type III-N capping layer over the p-type III-N body layer. A source electrode that contacts the n-type III-N capping layer is electrically connected to the p-type III-N body layer and is electrically isolated from the 2DEG channel when the gate electrode is biased relative to the source electrode at a voltage that is below a threshold voltage.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack structure of a quantum dot device, wherein the quantum well stack structure includes an insulating material to define multiple rows of quantum dot formation regions; and a gate that extends over multiple ones of the rows.

A semiconductor structure includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a first passivation layer on the insulating layer, a contact structure disposed on the first passivation layer and extending through the first passivation layer to directly contact a portion of the barrier layer, and an insulating layer interposed between the barrier layer and the first passivation layer and comprising an extending portion protruding toward a bottom corner of the contact structure.

Described herein are lateral III-N (e.g., GaN) devices having a III-N depleting layer. A circuit includes a depletion-mode transistor with a source connected to a drain of an enhancement-mode transistor. The gate of the depletion-mode transistor and the gate of the enhancement-mode transistor are biased at zero volts, and the drain of the depletion-mode transistor is biased at positive voltage to block a current in a forward direction. Then, the bias of the gate of the enhancement-mode transistor is changed to a first voltage greater than the threshold voltage of the enhancement-mode transistor and a first current is allowed to flow through the channel in a forward direction. Then, the bias of the gate of the depletion-mode transistor is changed to a second voltage and a second current is allowed to flow through the channel in a forward direction where the second current is greater than the first current.

Methods for the manufacture of semiconductor devices with integrated two-dimensional (2D) materials are disclosed. Aspects can include forming a base structure comprising a seed material with a chemical element; forming source/drain contacts coupled to first and second portions of the base structure, respectively, wherein the source/drain contacts each have at least the chemical element; exposing a third portion of the base structure; selectively growing a 2D material at least coupled to the third portion of the base structure; and forming an active gate coupled to the 2D material.

A method for forming a semiconductor structure includes the steps of forming a stacked structure on a substrate, forming an insulating layer on the stacked structure, forming a passivation layer on the insulating layer, performing an etching process to form an opening through the passivation layer and the insulating layer to expose a portion of the stacked structure and an extending portion of the insulating layer, and forming a contact structure filling the opening and directly contacting the stacked structure, wherein the extending portion of the insulating layer is adjacent to a surface of the stacked structure directly contacting the contact structure.

A production method for a semiconductor device includes: forming a first nitride semiconductor layer having nitrogen polarity at upper surface; forming a first dielectric film on the first nitride semiconductor layer; forming a first opening in the first dielectric film, part of the first nitride semiconductor layer being exposed from the first opening; forming a second nitride semiconductor layer inward of the first opening and on the first nitride semiconductor layer; forming a second opening in the first dielectric film after the formation of the second nitride semiconductor layer, part of the first nitride semiconductor layer being exposed from the second opening; forming a second dielectric film inward of the second opening and on the first nitride semiconductor layer; forming an ohmic electrode that is in an ohmic contact with the second nitride semiconductor layer; and forming a gate electrode above the second opening and on the second dielectric film.

A semiconductor device includes a semiconductor structure forming a carrier channel, a barrier layer arranged in proximity with the semiconductor structure, and a set of electrodes for providing and controlling carrier charge in the carrier channel. The barrier layer is at least partially doped by impurities having a conductivity type opposite to a conductivity type of the carrier channel. The material of the barrier layer has a bandgap and thermal conductivity larger than a bandgap and thermal conductivity of material in the semiconductor structure.

A transistor, a display device, and associated methods, the transistor including a substrate; an active layer pattern disposed on the substrate, the active layer pattern including silicon and graphene; a gate insulating layer disposed on the active layer pattern; a gate electrode disposed on the gate insulating layer; an insulating interlayer covering the active layer pattern and the gate electrode; and a source electrode and a drain electrode in contact with the active layer pattern.