As means for preventing a leakage of a fuse element cut by laser trimming due to a conductive residue or the like, an insulating film which has a high thermal conductivity and a relatively low adhesion is formed between an element isolation region and the fuse element in the case of forming the fuse element on the element isolation region in a groove on a main surface of an epitaxial substrate. When the fuse element is cut by performing the laser trimming, both of a part of the fuse element and the insulating film below the part of the fuse element are removed.

A semiconductor device is provided, including: a semiconductor substrate; an active portion provided on the semiconductor substrate; a first well region and a second well region provided on the semiconductor substrate and arranged sandwiching the active portion in a top view; a peripheral well region provided on the semiconductor substrate and arranged enclosing the active portion in a top view; an intermediate well region provided on the semiconductor substrate and arranged between the first well region and the second well region in a top view; a first pad arranged above the first well region and a second pad arranged above the second well region; and a temperature sense diode arranged above the intermediate well region.

A semiconductor device includes a semiconductor substrate, an insulating film, a first coil, a second coil, a third coil, a fourth coil, a first guard ring and a second guard ring. The first coil and the second coil are formed on the semiconductor substrate. The third coil faces the first coil through the insulating film. The fourth coil faces the second coil through the insulating film. The first guard ring is formed to surround the third coil in plan view. The second guard ring is formed to surround the fourth coil in plan view. The first guard ring and the second guard ring are adjacent to each other while being spaced apart from each other in plan view.

A semiconductor device includes a protection element configured by a MOSFET, and the protection element has a multilayer metal wiring structure. The multilayer metal wiring structure includes drain connection wirings connected to drain regions of the MOSFET and source connection wirings connected to source regions of the MOSFET. In a part of a layer of the multilayer metal wiring structure where both the drain connection wirings and the source connection wirings are present, only either the drain connection wirings or the source connection wirings are laid out in a grained pattern.

A semiconductor device according to the present disclosure includes: a semiconductor substrate with a first main surface and a second main surface; a drift layer of a first conductivity type formed in the semiconductor substrate; a first impurity diffusion layer of a second conductivity type formed on the drift layer to be closer to the first main surface; and a buffer layer of the first conductivity type formed on the drift layer to be closer to the second main surface and higher in peak impurity concentration than the drift layer. The drift layer has a first trap, a second trap, and a third trap, whose energy level each is lower than energy at a bottom of a conduction band by 0.246 eV, 0.349 eV, and 0.470 eV. The second trap has trap density of equal to or greater than 2.010.sup.11 cm.sup.3.

The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich isolation region and methods of manufacture. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap rich isolation region embedded within a substrate underneath both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.

An open base transistor has an emitter region of a first doping polarity, a collector region of the first doping polarity, a base region of a second polarity different from the first doping polarity, and an additional region of the first doping polarity. The base region is resistively connected to the additional region via a resistor.

In a semiconductor device, it is preferable to suppress a variation in characteristics of a temperature sensor. The semiconductor device is provided that includes a semiconductor substrate having a first conductivity type drift region, a transistor section provided in the semiconductor substrate, a diode section provided in the semiconductor substrate, a second conductivity type well region exposed at an upper surface of the semiconductor substrate, a temperature sensing unit that is adjacent to the diode section in top view and is provided above the well region, and an upper lifetime control region that is provided in the diode section, at the upper surface side of the semiconductor substrate, and in a region not overlapping with the temperature sensing unit in top view.

According to an aspect of the present disclosure, a semiconductor device includes a substrate including an IGBT region, and a diode region, a surface electrode provided on a top surface of the substrate and a back surface electrode provided on a back surface on an opposite side to the top surface of the substrate, wherein the diode region includes a first portion formed to be thinner than the IGBT region by the top surface of the substrate being recessed, and a second portion provided on one side of the first portion and thicker than the first portion.

A semiconductor device includes a bipolar device and a logic device adjacent the bipolar device. A backside of the bipolar device is connected to a backside interconnect. A frontside of the bipolar device is connected to a back end of line (BEOL).