To enhance the performance of a semiconductor device. In a method for manufacturing a semiconductor device, a metal film is formed over a semiconductor substrate having an insulating film formed on a surface thereof, and then the metal film is removed in a memory cell region, whereas, in a part of a peripheral circuit region, the metal film is left. Next, a silicon film is formed over the semiconductor substrate, then the silicon film is patterned in the memory cell region, and, in the peripheral circuit region, the silicon film is left so that an outer peripheral portion of the remaining metal film is covered with the silicon film. Subsequently, in the peripheral circuit region, the silicon film, the metal film, and the insulating film are patterned for forming an insulating film portion formed of the insulating film, a metal film portion formed of the metal film, and a conductive film portion formed of the silicon film.

An MISFET has a gate electrode formed on a semiconductor substrate via a gate insulating film, and a source region and a drain region formed inside the semiconductor substrate so as to sandwich the gate electrode. And, a first silicide layer is formed on surfaces of the source region and the drain region, and a second silicide layer is formed on a surface of the gate electrode. Each of the first silicide layer and the second silicide layer is made of a first metal and silicon, and further contains a second metal different from the first metal. And, a concentration of the second metal inside the second silicide layer is lower than a concentration of the second metal inside the first silicide layer.

The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density. The semiconductor device includes: first bit lines and an insulating layer that is provided between the first bit lines and in a groove. First faces of the first bit lines are aligned on a first line and second faces of the first bit lines are aligned on a second line. A first face of the insulating layer is disposed at a third line that is a first distance from the first line in a first direction and a second face of the insulating layer is disposed at a fourth line that is a second distance from the second line in a second direction.

A non-volatile memory includes a substrate region, a barrier layer, an N-type well region, an isolation structure, a first gate structure, a first sidewall insulator, a first P-type doped region, a second P-type doped region and an N-type doped region. The isolation structure is arranged around the N-type well region and formed over the barrier layer. The N-type well region is surrounded by the isolation structure and the barrier layer. Consequently, the N-type well region is an isolation well region. The first gate structure is formed over a surface of the N-type well region. The first sidewall insulator is arranged around the first gate structure. The first P-type doped region, the second P-type doped region and the N-type doped region are formed under the surface of the N-type well region.

An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.

Unwanted erosion of dielectric materials around a backside contact trench can be avoided or minimized employing an aluminum oxide liner. An aluminum oxide liner can be formed inside an insulating material layer in a backside contact trench to prevent collateral etching of the insulating material at an upper portion of the backside contact trench during an anisotropic etch that forms an insulating spacer. Alternatively, an aluminum oxide layer can be employed as a backside blocking dielectric layer. An upper portion of the aluminum oxide layer can be converted into an aluminum compound layer including aluminum and a non-metallic element other than oxygen at an upper portion of the trench, and can be employed as a protective layer during formation of a backside contact structure.

Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate structures disposed on the substrate. The active portions are spaced apart from each other in a first direction and extend in a second direction perpendicular to the first direction. The gate structures are spaced apart from each other in the second direction and extend in the first direction. Each of the device isolation patterns includes a first air gap, and each of a top surface and a bottom surface of the first air gap has a wave-shape in a cross-sectional view taken along the second direction.

An electrode having an embedded charge contains a substrate, a first electronic charge trap defined at the interface of a first insulating layer and a second insulating layer; and a first conductive layer disposed on the first electronic charge trap; wherein the first conductive layer contains a conductive material configured to permit an external electric field to penetrate the electrode from the first electronic charge trap; and wherein the first insulating layer is not the same as the second insulating layer.

A semiconductor device is provided in which the power consumption can be reduced by reducing the driving voltage and the on-state current can be increased in a period in which a transistor having an extremely low off-state current is brought into an electrically floating state. The semiconductor device comprises a memory cell, a first circuit, and a second circuit. The memory cell includes a first transistor. The first transistor includes a first semiconductor layer, a first gate electrode, and a first back gate electrode. The first gate electrode is connected to a word line. The first back gate electrode is connected to a back gate line. The first circuit supplies a signal for controlling the conduction state of the first transistor to the word line. The second circuit supplies a voltage for controlling the threshold voltage of the first transistor to the back gate line. The second circuit has a function of bringing the back gate line into an electrically floating state in a period in which a signal for controlling the conduction state of the first transistor is supplied to the word line.

A semiconductor device may include pillars and a plurality of conductive layers being stacked while surrounding the pillars and including a plurality of first regions including non-conductive material layers and a plurality of second regions including conductive material layers, wherein the first regions and the second regions are alternately arranged.