A semiconductor device according to an embodiment includes a SiC semiconductor layer, a gate electrode, a gate insulating film provided between the SiC semiconductor layer and the gate electrode, and a region that is provided between the SiC semiconductor layer and the gate insulating film and includes at least one element selected from the group consisting of antimony (Sb), scandium (Sc), yttrium (Y), lanthanum (La), and lanthanoids (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu). The concentration of the at least one element is equal to or greater than 110.sup.19 cm.sup.3 and equal to or less than 2.410.sup.22 cm.sup.3.

Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a method for forming a semiconductor device includes forming a first epitaxial layer on sidewalls of trenches and forming second epitaxial layer on the first epitaxial layer where charges in the doped regions along the sidewalls of the first and second trenches achieve charge balance in operation. In another embodiment, the semiconductor device includes a termination structure including an array of termination cells.

A manufacturing method includes an implantation of impurities and laser irradiation. In the implantation, impurities are implanted to first and second areas so as to obtain a relationship that a total amount of the first impurities is larger than a total amount of the second impurities in a first depth range and a total amount of the second impurities is larger than a total amount of the first impurities in a second depth range (deeper range). In the irradiation, the first and second areas are irradiated with laser so that an energy density of the laser is larger on the second area than on the first area. A first conductivity type region is formed on the first area so as to be exposed on the surface, and a second conductivity type region is formed on the second area so as to be exposed on the surface.

A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier, an isolation contact region disposed in the semiconductor substrate outside of the core device area, and a body region disposed in the semiconductor substrate within the core device area, and in which a channel is formed during operation. The body region is electrically tied to the isolation contact region. The body region and the doped isolation barrier have a common conductivity type. The body region is electrically isolated from the doped isolation barrier within the core device area. The doped isolation barrier and the isolation contact region are not electrically tied to one another such that the doped isolation barrier is biased at a different voltage level than the isolation contact region.

An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.

A high-quality nitride crystal can be produced efficiently by charging a nitride crystal starting material that contains tertiary particles having a maximum diameter of from 1 to 120 mm and formed through aggregation of secondary particles having a maximum diameter of from 100 to 1000 m, in the starting material charging region of a reactor, followed by crystal growth in the presence of a solvent in a supercritical state and/or a subcritical state in the reactor, wherein the nitride crystal starting material is charged in the starting material charging region in a bulk density of from 0.7 to 4.5 g/cm.sup.3 for the intended crystal growth.

Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.

A compound semiconductor device includes: a substrate; and a buffer layer, a first carrier supply layer, a first spacer layer, a channel layer, a second spacer layer, a second carrier supply layer, and a contact layer provided in order on the substrate, wherein the first carrier supply layer is a uniformly doped layer in which an impurity is uniformly doped, the second carrier supply layer is a planar doped layer in which an impurity is locally doped, and no Al mixed crystal layer having higher resistance values than the first and second spacer layers is provided between the buffer layer and the first spacer layer and between the second spacer layer and the contact layer.

The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate; a channel region of a first type conductivity, defined in the fin active region and having a first carrier concentration; and an anti-punch through (APT) feature of the first type conductivity, wherein the APT feature is formed in the semiconductor substrate, is directly underlying the channel region, and has a second carrier concentration greater than the first carrier concentration.

Some embodiments of the present disclosure relate to a transistor device formed in a semiconductor substrate containing dopant impurities of a first impurity type. The transistor device includes channel composed of a delta-doped layer comprising dopant impurities of the first impurity type, and configured to produce a peak dopant concentration within the channel. The channel further includes a layer of carbon-containing material overlying the delta-doped layer, and configured to prevent back diffusion of dopants from the delta-doped layer and semiconductor substrate. The channel also includes of a layer of substrate material overlying the layer of carbon-containing material, and configured to achieve steep retrograde dopant concentration profile a near a surface of the channel. In some embodiments, a counter-doped layer underlies the delta-doped layer configured to reduce leakage within the semiconductor substrate, and includes dopant impurities of a second impurity type, which is opposite the first impurity type.