Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first fin field effect transistor (FinFET) disposed over a substrate, and a second FinFET device disposed over the first FinFET. A junction isolation material is disposed between a source of the first FinFET and a source of the second FinFET.

A Group III-nitride-based enhancement mode transistor having a heterojunction fin structure and a corresponding semiconductor device are described.

A robust electrostatic (ESD) protection device is provided. In one example, the ESD protection device is configured to accommodate three nodes. When used with a differential signal device, the first and second nodes may be coupled with the differential signal device's BP and BM signal lines, respectively, and the third node may be coupled to a voltage source. This allows for a single ESD protection device to be used to protect the signal lines of the differential signal device, thus providing significant substrate area savings as compared to the conventional means of using three dual-node ESD protection devices to accomplish substantially the same protection mechanism. Moreover, the ESD protection device may be structurally designed to handle high voltage ESD events, as required by the FlexRay standard.

A semiconductor device includes transistor cells formed inside a semiconductor body. First and second semiconductor well regions have second conductivity type dopants and are arranged external of the transistor cells. The first semiconductor well region is arranged between two transistor cells and the second semiconductor well region is electrically connected with a load contact. A separation region has first conductivity type dopants and extends from a surface of the semiconductor body along the vertical direction and is arranged between and in contact with each of the first and second semiconductor well regions. The first semiconductor well region extends at least as deep as each of body regions of two transistor cells. A transition in a first lateral direction between the separation and first semiconductor well regions extends continuously from the surface to a point in the semiconductor body at least as deep as each body region of two transistor cells.

A semiconductor structure includes a first device and a second device. The first device has a first surface. The first device includes a first active region defined by a first material system. The second device has a second surface. The second surface is coplanar with the first surface. The second device includes a second active region defined by a second material system. The second material system is different from the first material system.

Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.

Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.

A driving circuit includes a first driver, a switching circuit and a second driver. The first driver receives and input signal and an inverted input signal, and generates a driving signal. The switching circuit receives the driving signal and a first mode signal. Moreover, an output signal is outputted from an output terminal. The second driver is connected with the output terminal.

A semiconductor device of the present invention includes a semiconductor layer, a plurality of gate trenches formed in the semiconductor layer, a gate electrode filled via a gate insulating film in the plurality of gate trenches, an n.sup.+-type emitter region, a p-type base region, and an n.sup.-type drift region disposed, lateral to each gate trench, in order in a depth direction of the gate trench from a front surface side of the semiconductor layer, a p.sup.+-type collector region disposed on a back surface side of the semiconductor layer with respect to the n.sup.-type drift region, a plurality of emitter trenches formed between the plurality of gate trenches adjacent to each other, a buried electrode filled via an insulating film in the plurality of emitter trenches, and electrically connected with the n.sup.+-type emitter region, and a p-type floating region formed between the plurality of emitter trenches, and the p-type floating region is formed deeper than the p-type base region, and includes an overlap portion that goes around to a lower side of an emitter trench closest to the gate trench out of the plurality of emitter trenches and has an end portion positioned on a side closer to the gate trench with respect to a center in a width direction of the emitter trench.

In a semiconductor device, a lightly doped second semiconductor layer of a first conductive type is joined with a heavily doped first semiconductor layer of the first conductive type. A power transistor having a first conductive type channel and a transistor are formed in surface regions of the second semiconductor layer, respectively. A first diffusion layer of a second conductive type is formed in a surface region of the second semiconductor layer to provide a boundary between the power transistor and the transistor. The first semiconductor layer functions as a drain of the power transistor. The first diffusion layer region is set to the same voltage as that of the drain.