In a general aspect, an apparatus can include a silicon carbide (SiC) trench gate MOSFET with improved operation due, at least in part, to a reduced gate capacitance. In the SiC trench gate MOSFET, a thick gate oxide can be formed on a bottom surface of the gate trench and a built-in channel, having a vertical portion and a lateral portion, can be formed to electrically connect a vertical inversion-layer channel, such as in a channel stopper layer, to a vertical JFET channel region and a drift region.

In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.

An on-resistance of a junction FET is reduced. In a semiconductor device in an embodiment, a gate region of the junction field effect transistor includes a low concentration gate region and a high concentration gate region whose impurity concentration is higher than an impurity concentration of the low concentration gate region, and the high concentration gate region is included in the low concentration gate region.

A vertical junction field effect transistor (JFET) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate doped with a first conductivity-type dopant. A fin of semiconductor material doped with the first conductivity-type dopant has a first end in contact with the source region and further includes a second end and sidewalls between the first and second ends. A drain region is formed of first epitaxial material grown from the second end of the fin and doped with the first conductivity-type dopant. A gate structure is formed of second epitaxial material grown from the sidewalls of the fin and doped with a second conductivity-type dopant.

A nitride semiconductor device includes: a substrate; a drift layer, a high-resistance layer, and a first base layer above the substrate in stated order; a gate opening penetrating through the first base layer and the high-resistance layer to the drift layer; an electron transport layer and an electron supply layer covering an upper portion of the first base layer and the gate opening; a gate electrode above the electron supply layer; a source electrode in contact with the electron supply layer; an electrode opening penetrating through the electron supply layer and the electron transport layer to the first base layer; a potential fixing electrode in contact with the first base layer at a bottom part of the electrode opening; and a drain electrode below the substrate.

A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.

Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.

A semiconductor device includes a substrate and a drift layer on the substrate, the drift layer having a first conductivity type. The device includes a first plurality of vertical junction field effect (JFET) subcells and a second plurality of vertical JFET subcells on the drift layer. The first plurality of vertical JFET subcells are connected in parallel to form a first JFET device, and the second plurality of vertical JFET subcells are connected in parallel to form a second JFET device. The second JFET device is connected in anti-series with the first JFET device through the drift layer. The device further includes a first gate electrode and a first current terminal in contact with the first plurality of vertical JFET subcells, and a second gate electrode and a second current terminal in contact with the second plurality of vertical JFET subcells.

Disclosed are a vertical coupling capacitance gate-controlled junction field effect transistor and a manufacturing method thereof. The vertical coupling capacitance gate-controlled junction field effect transistor includes a base of a first doping type; two bottom gates of the second doping type, formed inside the base and spaced apart in the lateral direction; a top gate of the second doping type, formed inside the base, where the top gate is located above the interval between the two bottom gates, and an interval is formed between the top gate and the bottom gate; a dielectric layer, formed on the base and located on the top gate; and a coupling capacitance upper electrode, formed on the dielectric layer; where the top gate is indirectly controlled by the coupling capacitance upper electrode spaced with the dielectric layer.

Disclosed are a vertical trench coupling capacitance gate-controlled junction field effect transistor and a manufacturing method thereof. The vertical trench coupling capacitance gate-controlled junction field effect transistor includes a substrate of a first doping type, an epitaxial layer of the first doping type, and a plurality of repeating units disposed adjacently; where the epitaxial layer is disposed on the substrate, the substrate is served as a drain region, and each of the repeating units includes: two source regions of the first doping type; a trench; a gate of the second doping type; a dielectric; and a coupling capacitance upper electrode, where the gate is indirectly controlled by the coupling capacitance upper electrode spaced with the dielectric layer.