A field-effect transistor with a buried gate, and a method of making the same. A volume of semiconductor material includes first and second ends and left and right sides. A source is located at the first end, a drain is provided, a left first gate structure is located at the left side, and a right first gate structure is located at the right side. A second, buried gate is located between and spaced apart from the source and the drain and the left and right first gate structures so as to be surrounded in first and second dimensions by the semiconductor material. The second gate divides a channel into multiple paths for current to flow between the source and the drain. The second gate includes a projection extending in a third dimension and presenting an exposed surface operable to receive a voltage.

The planar junction field-effect transistor provides enhanced channel control. A method of making such a JFET is also disclosed. A volume of semiconductor material includes a first end and a second end, a source and a first gate are located at the first end, a drain is spaced apart from the source, and a channel is provided between the source and the drain. A second gate is located between the source and drain so as to be surrounded, or buried, in a first dimension and a second dimension by the semiconductor material, and thereby divides the channel into multiple non-linear channel paths. The gates cooperatively determine the channel paths and enhance the channel control. The second gate may include an extension in a third dimension through the semiconductor material. The extension may present an exposed surface for an electrical terminal for receiving a voltage.

A mesa junction field-effect transistor is provided with channel engineering, and a method of making such a device is disclosed. A volume of semiconductor material includes a first end, a second end, a first side, and a second side. A channel extends between a source located at the first end and a drain. A first gate is located at the first side. A second gate is located at the second side, opposite the first gate, and includes upper and lower components located along an opposite side of the channel. The lower second gate component is spaced below and extends beneath the source, thereby creating at least two turns in the channel. The first and second gates cooperate to provide multiple control points in the non-linear channel for controlling electrical current flowing through the channel.

A trench junction field effect transistor (trench JFET) includes a mesa region confined by first and second trenches along a first lateral direction. The first and second trenches extend into a semiconductor body from a first surface of the semiconductor body. A mesa channel region of a first conductivity type is confined, along the first lateral direction, by first and second gate regions of a second conductivity type. A first pn junction is defined by the mesa channel region and the first gate region. A second pn junction is defined by the mesa channel region and the second gate region. The mesa channel region includes, along the first lateral direction, first, second and third mesa channel sub-regions having a same extent along the first lateral direction.

A junction field-effect transistor device includes an integrated temperature sensor, and a method of making the same is disclosed. A temperature sensor material having a first charge carrier polarity is implanted into an area of semiconductor material having a second charge carrier polarity, with the area being located adjacent to the junction field-effect transistor. The sensor material contains dopants and exhibits an electrical resistance that increases with a number of ionized ones of the dopants. The number of ionized dopants increases with the temperature of the material. First and second electrical terminals are provided spaced-apart on the sensor material for measuring the electrical resistance of the material. The measured electrical resistance may be translated into a temperature value for the junction field-effect transistor.

Embodiments of the present disclosure illustrate a semiconductor device. The semiconductor device comprises a silicon carbide epitaxial layer, comprising: a p-type well region; a junction field effect region adjacent to the p-type well region; a heavily doped n-type region on a surface of the p-type well region; and a heavily doped p-type region below the heavily doped n-type region and within the p-type well region. The semiconductor device further comprises an island-shaped oxide layer on the junction field effect region; a gate oxide layer covering the p-type well region, the junction field effect region, the heavily doped n-type region, the heavily doped p-type region and the island-shaped oxide; and a polycrystalline silicon layer on the gate oxide layer without contacting the island-shaped oxide.

A method includes providing a two-level gallium nitride (GaN) epitaxial substrate comprising a first GaN drift layer characterized by a first doping concentration and a second GaN drift layer disposed on the first GaN drift layer and characterized by a second doping concentration higher than the first doping concentration and forming a plurality of pedestals in the second GaN drift layer. Each of the plurality of pedestals is laterally separated by one of a plurality of funnels. The method also includes performing a channel regrowth process to regrow a plurality of n-type GaN channels, each disposed in one of the plurality of funnels, and performing a gate regrowth process to regrow p-type GaN. The method further includes patterning the p-type GaN to form a plurality of p-type GaN gates disposed in one of the plurality of n-type GaN channels, and forming source contacts, gate contacts, and a drain contact.