Patent classifications
H10F39/107
Semiconductor photomultiplier
The present disclosure relates to a semiconductor photomultiplier comprising a substrate; an array of photosensitive cells formed on the substrate that are operably coupled between an anode and a cathode. A set of primary bus lines are provided each being associated with a corresponding set of photosensitive cells. A secondary bus line is coupled to the set of primary bus lines. An electrical conductor is provided having a plurality of connection sites coupled to respective connection locations on the secondary bus line for providing conduction paths which have lower impedance than the secondary bus line.
RANGING DEVICE READ-OUT CIRCUIT
A ranging device includes an array of photon detection devices that receive an optical signal reflected by an object in an image scene and first and second logic devices to respectively combine the outputs of first and second pluralities of the photon detection devices. First and second counter circuits are respectively coupled an output of the first and second logic devices and generate first and second count values respectively by counting the photon detection events generated by the first and second pluralities of photon detection devices. A range estimation circuit estimates the range of the object by estimating the timing of one or more pulses of said optical signal based on the first and second count values.
RANGING DEVICE WITH IMAGING CAPABILITY
A ranging device includes an array of photon detection devices adapted to receive an optical signal reflected by an object in an image scene. First and second logic devices are adapted to respectively combine the outputs of first and second pluralities of the photon detection devices. A first range detection circuit is coupled to outputs of the first and second logic devices and a first counter is coupled to the output of the first logic device and adapted to generate a first pixel value by counting events generated by the first plurality of photon detection devices. A second counter is coupled to the output of the second logic device and is adapted to generate a second pixel value by counting events generated by the second plurality of photon detection devices. The first and second pixel values may be used in estimating a range to the object in the image scene.
Manufacturing method of sensing integrated circuit
A manufacturing method of a sensing integrated circuit including the following acts. A plurality of transistors are formed. At least one dielectric layer is formed on or above the transistors. A plurality of connecting structures are formed in the dielectric layer. The connecting structures are respectively and electrically connected to the transistors. A plurality of separated conductive wells are respectively formed in electrical contact with the connecting structures.
BISPECTRAL MATRIX SENSOR AND METHOD FOR MANUFACTURING THE SAME
The present invention relates to a method for manufacturing a bispectral matrix detector comprising the following steps: providing a monotype matrix detector; depositing, on the sensitive surface (3) of the monotype matrix detector, a dual-band interference filter (5) allowing the radiation in the first and second frequency bands to pass therethrough; depositing a first interference filter (4a) vertically in line with photosites (31a) intended for sensing in the first frequency band; depositing a second interference filter (4b) vertically in line with photosites (31b) intended for sensing in the second frequency band, one of the first (4a) and second (4b) interference filters being a low-pass filter cutting the second frequency band, and the other a high-pass filter cutting the first frequency band.
FRONT-ILLUMINATED PHOTOSENSITIVE LOGIC CELL
Photosensitive logic cell on a semiconductor-on-insulator substrate, possessing a P type transistor and an N type transistor fabricated on the front face of the substrate and whose respective threshold voltages can be modulated according to the quantity of photons received by a photosensitive zone provided opposite these transistors, the photosensitive zone possessing a photo-detection region whose arrangement is such that it favours illumination by the face of the photosensitive zone.
PHOTODIODE ARRAYS
A photodiode includes a cap layer defining an inboard side and an outboard side. A plurality of pixels are formed in the cap layer extending from the inboard side to the outboard side. At least a portion of the cap layer is defined in between the pixels. A metal barrier is in between the pixels and is operatively connected to the inboard side of the cap layer in between the pixels to reflect light rays into the cap layer reducing the leakage of photons between the pixels.
QUANTUM EFFICIENCY (QE) RESTRICTED INFRARED FOCAL PLANE ARRAYS
A sensor includes an InGaAs photodetector configured to convert received infrared radiation into electrical signals. A notch filter is operatively connected to the InGaAs photodetector to block detection of wavelengths within at least one predetermined band. An imaging camera system includes an InGaAs photodetector configured to convert received infrared radiation into electrical signals, the InGaAs photodetector including an array of photodetector pixels each configured to convert infrared radiation into electrical signals for imaging. At least one optical element is optically coupled to the InGaAs photodetector to focus an image on the array. A notch filter is operatively connected to the InGaAs photodetector to block detection of wavelengths within at least one predetermined band. A ROIC is operatively connected to the array to condition electrical signals from the array for imaging.
Integration of photonic, electronic, and sensor devices with SOI VLSI microprocessor technology
According to an aspect of the present principles, methods are provided for fabricating an integrated structure. A method includes forming a very large scale integration (VLSI) structure including a semiconductor layer at a top of the VLSI structure. The method further includes mounting the VLSI structure to a support structure. The method additionally includes removing at least a portion of the semiconductor layer from the VLSI structure. The method also includes attaching an upper layer to the top of the VLSI structure. The upper layer is primarily composed of a material that has at least one of a higher resistivity or a higher transparency than the semiconductor layer. The upper layer includes at least one hole for at least one of a photonic device or an electronic device. The method further includes releasing said VLSI structure from the support structure.
INTEGRATED BOUND-MODE SPECTRAL/ANGULAR SENSORS
A 2-D sensor array includes a semiconductor substrate and a plurality of pixels disposed on the semiconductor substrate. Each pixel includes a coupling region and a junction region, and a slab waveguide structure disposed on the semiconductor substrate and extending from the coupling region to the region. The slab waveguide includes a confinement layer disposed between a first cladding layer and a second cladding layer. The first cladding and the second cladding each have a refractive index that is lower than a refractive index of the confinement layer. Each pixel also includes a coupling structure disposed in the coupling region and within the slab waveguide. The coupling structure includes two materials having different indices of refraction arranged as a grating defined by a grating period. The junction region comprises a p-n junction in communication with electrical contacts for biasing and collection of carriers resulting from absorption of incident radiation.