A method comprises providing a substrate with a second conductivity type, growing a first epitaxial layer having the second conductivity type, growing a second epitaxial layer having a first conductivity type, forming a trench in the first epitaxial layer and the second epitaxial layer, forming a gate electrode in the trench, applying an ion implantation process using first gate electrode as an ion implantation mask to form a drain-drift region, forming a field plate in the trench, forming a drain region in the second epitaxial layer, wherein the drain region has the first conductivity type and forming a source region in the first epitaxial layer, wherein the source region has the first conductivity type, and wherein the source region is electrically coupled to the field plate.

A semiconductor device includes a first semiconductor layer of a first conductivity type formed on one side of a semiconductor substrate; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer; a third semiconductor layer of the first conductivity type formed on the second semiconductor layer; an opening part formed by removing part of the first to third semiconductor layers; a gate insulating film formed so as to cover an inner wall of the opening part; a gate electrode formed inside the opening part via the gate insulating film; a source electrode formed on a surface of the third semiconductor layer; a drain electrode connected to a part corresponding to the gate electrode on another side of the semiconductor substrate; and a fourth electrode formed on the another side of the semiconductor substrate at a part corresponding to the source electrode.

A tri-gate laterally-diffused metal oxide semiconductor (LDMOS), including a substrate, a P-type semiconductor region, a P-type contact region, an N-type source region, a gate dielectric layer, an N-type drift region, a first isolation dielectric layer, an N-type drain region, and a second isolation dielectric layer. The P-type semiconductor region is disposed on one end of an upper surface of the substrate, and the N-type drift region is disposed on another end of the upper surface. The P-type semiconductor region contacts with the N-type drift region. The P-type contact region and the N-type source region are disposed on one side of the P-type semiconductor region which is away from the N-type drift region, and compared with the P-type contact region, the N-type source region is in the vicinity of the N-type drift region.

A method for producing a semiconductor power device, includes forming a gate trench from a surface of a semiconductor layer toward an inside thereof. A first insulation film is formed on an inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO.sub.2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.

To more easily form a structure that mitigates the electrical field focus at the bottom portion of the trench gate and prevents decreases and variations in the gate threshold value (V.sub.th), provided is a semiconductor device including a semiconductor substrate; a second semiconductor region with a second conduction type that is provided above the semiconductor substrate and includes a first semiconductor region with a first conduction type in a portion thereof; a third semiconductor region that is provided above the second semiconductor region and has a higher second conduction type impurity concentration than the second semiconductor region; and a gate trench that penetrates through the third semiconductor region and is provided on top of the first semiconductor region. The gate trench includes a gate insulating film provided on side walls and a bottom portion of the gate trench and a gate electrode provided in contact with the gate insulating film.

A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface. the device also includes a gate located on the major surface. The device further includes a drain region having a first conductivity type. The device also includes a source region having the first conductivity type, wherein the source region is located within a region having a second conductivity type. The device further includes a channel region comprised of a part of the region having the second conductivity type that is located beneath the gate. The drain region extends laterally away from the gate along the major surface of the substrate. The drain also extends beneath the gate, the source region and the region having the second conductivity type to isolate the source region and the region having the second conductivity type from an underlying region of the substrate.

Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a method for forming a semiconductor device includes forming a first epitaxial layer on sidewalls of trenches and forming second epitaxial layer on the first epitaxial layer where charges in the doped regions along the sidewalls of the first and second trenches achieve charge balance in operation. In another embodiment, the semiconductor device includes a termination structure including an array of termination cells.

Provided is a semiconductor and method of manufacturing the same, and a method of forming even doping concentration of respective semiconductor device when manufacturing multiple semiconductor devices. When a concentration balance is disrupted due to an increase in doping region size, doping concentration is still controllable in example by using ion injected blocking pattern. Thus, the examples relate to a semiconductor and manufacture device with even doping, and high breakdown voltage obtainable as a result of such doping.

In one embodiment, a RESURF structure between a source and a drain in a lateral MOSFET is formed in a trench having a flat bottom surface and angled sidewalls toward the source. Alternating P and N-type layers are epitaxially grown in the trench, and their charges balanced to achieve a high breakdown voltage. In the area of the source, the ends of the P and N-layers angle upward to the surface under the lateral gate and contact the body region. Thus, for an N-channel MOSFET, a positive gate voltage above the threshold forms a channel between the source and the N-layers in the RESURF structure as well as creates an inversion of the ends of the P-layers near the surface for low on-resistance. In another embodiment, the RESURF structure is vertically corrugated by being formed around trenches, thus extending the length of the RESURF structure for a higher breakdown voltage.

An n.sup. drift region is disposed on the front surface of an n.sup.+ semiconductor substrate composed of a wide band gap semiconductor. A p-channel region is selectively disposed on the surface layer of the n.sup. drift region. A high-concentration p.sup.+ base region is disposed so as to adjoin the lower portion of the p-channel region inside the n.sup. drift region. Inside the high-concentration p.sup.+ base region, an n.sup.+ high-concentration region is selectively disposed at the n.sup.+ semiconductor substrate side. The n.sup.+ high-concentration region has a stripe-shaped planar layout extending to the direction that the high-concentration p.sup.+ base regions line up. The n.sup.+ high-concentration region adjoins a JFET region at one end portion in longitudinal direction of the stripe. Further, the n.sup.+ semiconductor substrate side of the n.sup.+ high-concentration region adjoins the part sandwiched between the high-concentration p.sup.+ base region and the n.sup.+ semiconductor substrate in the n.sup. drift region.