A device includes a semiconductor substrate, source and drain regions disposed in the semiconductor substrate and having a first conductivity type, a body region disposed in the semiconductor substrate, having a second conductivity type, and in which the source region is disposed, a drift region disposed in the semiconductor substrate, having the first conductivity type, and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions, a device isolation region disposed in the semiconductor substrate and laterally surrounding the body region and the drift region, and a breakdown protection region disposed between the device isolation region and the body region and having the first conductivity type.

A semiconductor device includes a gate structure located on a substrate and a raised source/drain region adjacent to the gate structure. The raised source/drain region includes: a first epitaxial-grown doped layer of the raised source/drain region in contact with the substrate; a second epitaxial-grown doped layer on the first epitaxial-grown doped layer and including a same dopant species as the first epitaxial-grown doped layer, wherein the second epitaxial-grown doped layer includes a higher dopant concentration than the first epitaxial-grown doped layer and interfacing the gate structure by using a predetermined distance; and a third epitaxial-grown doped layer on the second epitaxial-grown doped layer and including the same dopant species as the first epitaxial-grown doped layer, wherein the third epitaxial-grown doped layer includes a higher dopant concentration than the second epitaxial-grown doped layer.

A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.

High-voltage semiconductor device and method of forming the same, the high-voltage semiconductor device includes a substrate, a gate structure, a drain, a first insulating structure and a drain doped region. The gate structure is disposed on the substrate. The drain is disposed in the substrate, at one side of the gate structure. The first insulating structure is disposed on the substrate, under the gate structure to partially overlap with the gate structure. The drain doped region is disposed in the substrate, under the drain and the first insulating structure, and the drain doped region includes a discontinuous bottom surface.

A semiconductor structure includes a substrate, a deep well, a doped region, a field oxide, a gate structure, a source region, and a drain region. The deep well is with a first impurity of a first conductivity type in the substrate. The doped region is with a second impurity of a second conductivity type in the deep well, the second conductivity type being opposite to the first conductivity type. The field oxide partially is embedded in the deep well, wherein the field oxide interfaces with the doped region. The gate structure is over the field oxide and laterally extends across the doped region. The source region and the drain region laterally are separated at least in part by the doped region and the field oxide.

Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming a structure for a laterally-diffused metal-oxide-semiconductor device. The structure comprises a drain and a source in a semiconductor substrate. The source includes a source region having a first terminating end, a second terminating end, and a length between the first terminating end and the second terminating end. The structure further comprises a shallow trench isolation region in the semiconductor substrate. The shallow trench isolation region surrounds the drain. The structure further comprises a gate that surrounds the shallow trench isolation region and the drain. The gate has a side section between the drain and the source region, the side section of the gate has a width, and the gate has a length in a direction transverse to the width. The length of the source region is substantially equal to the length of the gate.

A semiconductor device including a semiconductor layer and a trench gate structure is provided. The semiconductor layer includes: a source region, a drift region, and a body region. The first part of the body region is located between the source region and the drift region, the first part of the body region and the source region both adjoin a first sidewall of the trench gate structure. The third part of the body region is located between a bottom surface of the trench gate structure and the second surface, at least part of the bottom surface of the trench gate structure is separated from the third part of the body region by the drift region. By separating the third part of the body region from the bottom surface along a vertical direction, electric field distribution at a bottom of a trench and near corner is adjusted.

Embodiments include mixed complementary field effect and unipolar transistors and methods of forming the same. In an embodiment, a structure includes: a first semiconductor nanostructure; a second semiconductor nanostructure; a first isolation structure interposed between the first semiconductor nanostructure and the second semiconductor nanostructure; a first source/drain region extending laterally from an end of the first semiconductor nanostructure, the first source/drain region having a first conductivity type; a second source/drain region extending laterally from an end of the second semiconductor nanostructure, the second source/drain region having the first conductivity type, the second source/drain region aligned vertically with the first source/drain region; and a first gate structure surrounding the first semiconductor nanostructure and the second semiconductor nanostructure.

A semiconductor structure includes first fins each extending lengthwise along a first direction, first source/drain epitaxial features disposed on the first fins, second fins each extending lengthwise along the first direction, second source/drain epitaxial features disposed on the second fins, and a separation structure disposed between the first fins and the second fins. The separation structure extends lengthwise along a second direction different from the first direction. Measured along the second direction, a width of one of the first fins is greater than a width of one of the second fins.

A lateral-conduction MOSFET device includes a semiconductor body and source regions of a first conductivity type extending into the body along a first direction at a distance from each other along a second (transverse) direction. Each source region has a first portion and a second portion along the first direction. Body contact regions, distinct from each other, one for each source region, of a second conductivity type extend into the body alongside and in contact with the respective first portion parallel to the second direction. The first portion of each source region and the respective body contact region together have a first width along the second direction. The second portion of each source region has a respective second width along the second direction. The first width is greater than the second width.