Patent classifications
H01L39/22
QUANTUM COUPLER FACILITATING SUPPRESSION OF ZZ INTERACTIONS BETWEEN QUBITS
Devices and/or computer-implemented methods to facilitate ZZ cancellation between qubits are provided. According to an embodiment, a device can comprise a coupler device that operates in a first oscillating mode and a second oscillating mode. The device can further comprise a first superconducting qubit coupled to the coupler device based on a first oscillating mode structure corresponding to the first oscillating mode and based on a second oscillating mode structure corresponding to the second oscillating mode. The device can further comprise a second superconducting qubit coupled to the coupler device based on the first oscillating mode structure and the second oscillating mode structure.
Circuit assembly, a system and a method for cooling quantum electric devices
A circuit assembly for cooling a quantum electrical device, use of said circuit assembly, a system and a method for cooling a quantum electric device are provided. The circuit assembly comprises a quantum electric device to be cooled, at least one normal-metal-insulator-superconductor (NIS) tunnel junction electrically connected to the quantum electric device and at least one superconductive lead for supplying a drive voltage V.sub.QCR for said at least one NIS tunnel junction. The quantum electric device is cooled when the voltage V.sub.QCR is supplied to at least one NIS tunnel junction, said voltage V.sub.QCR being equal to or below the voltage NΔ/e, where N=1 or N=2, N is the number of NIS tunnel junctions electrically coupled in series with the means for generating the voltage, Δ is the energy gap in the superconductor density of states, and e is the elementary charge.
Ferrimagnetic/ferromagnetic exchange bilayers for use as a fixed magnetic layer in a superconducting-based memory device
A magnetic Josephson junction (MJJ) device having a ferrimagnetic/ferromagnetic (FIM/FM) exchange-biased bilayer used as the magnetic hard layer improves switching performance by effectively sharpening the hysteresis curve of the device, thereby reducing error rate when the device is used in a Josephson magnetic random access memory (JMRAM) memory cell. Thus, the materials and devices described herein can be used to build a new type of MJJ, termed a ferrimagnetic Josephson junction (FIMJJ), for use in JMRAM, to construct a robust and reliable cryogenic computer memory that can be used for high-speed superconducting computing, e.g., with clock speeds in the microwave frequency range.
Semiconductor-superconductor hybrid device and its fabrication
A method of fabricating a semiconductor-superconductor hybrid device comprises providing a workpiece comprising a semiconductor component, a layer of a first superconductor material on the semiconductor component, and a layer of a second superconductor material on the first superconductor material, the second superconductor material being different from the first superconductor material; etching the layer of the second superconductor material to expose a portion of the first superconductor material; and oxidising the portion of the first superconductor material to form a passivating layer on the semiconductor. The first superconductor provides energy coupling between the semiconductor and the second superconductor, and the passivating layer protects the semiconductor while allowing electrostatic access thereto. Also provided are a hybrid device, and a method of etching.
METHOD FOR THE IN SITU PRODUCTION OF MAJORANA MATERIAL SUPERCONDUCTOR HYBRID NETWORKS AND TO A HYBRID STRUCTURE WHICH IS PRODUCED USING THE METHOD
A method for producing a hybrid structure, the hybrid structure including at least one structured Majorana material and at least one structured superconductive material arranged thereon includes producing, on a substrate, a first mask for structured application of the Majorana material and a further mask for structured growth of the at least one superconductive material, which are aligned relatively to one another, and applying the at least one structured superconductive material to the structured Majorana material with the aid of the further mask. The structured application of the Majorana material and of the at least one superconductive material takes place without interruption in an inert atmosphere.
Layered Hybrid Quantum Architecture for Quantum Computing Applications
A quantum system includes a qubit array comprising a plurality of qubits. A bus resonator is coupled between at least one pair of qubits in the qubit array. A switch is coupled between the at least one qubit pair of qubits.
SUPERCONDUCTING QUBIT LIFETIME AND COHERENCE IMPROVEMENT VIA BACKSIDE ETCHING
A method for improving lifetime and coherence time of a qubit in a quantum mechanical device is provided. The method includes providing a substrate having a frontside and a backside, the frontside having at least one qubit formed thereon, the at least one qubit having capacitor pads. The method further includes at least one of removing an amount of substrate material from the backside of the substrate at an area opposite the at least one qubit or depositing a superconducting metal layer at the backside of the substrate at the area opposite the at least one qubit to reduce radiofrequency electrical current loss due to at least one of silicon-air (SA) interface, metal-air (MA) interface or silicon-metal (SM) interface so as to enhance a lifetime (T1) and a coherence time (T2) in the at least one qubit.
QUANTUM DEVICE
A quantum device according to an example embodiment includes a quantum chip 10, and an interposer 20 on which the quantum chip 10 is mounted, in which the interposer 20 includes a conductive wiring line CL1 electrically connected to the quantum chip 10, a mounting surface 21 of the interposer 20 on which the quantum chip 10 is mounted or an opposite surface 22 opposite to the mounting surface 21 includes a first area AR11 and a second area AR12 different from the first area AR11 as viewed in a direction perpendicular to the mounting surface 21 or the opposite surface 22, the conductive wiring line CL1 is disposed in the first area AR11 on the mounting surface 21 or the opposite surface 22, and a movable member 60 is in contact with the second area AR12 of the interposer 20.
Digital Circuits Comprising Quantum Wire Resonant Tunneling Transistors
A digital circuit includes at least one quantum wire resonant tunneling transistor that includes an emitter terminal, a base terminal, a collector terminal, an emitter region in connection with the emitter terminal, a base region in connection with the base terminal, a collector region in connection with the collector terminal, an emitter barrier region between the emitter region and the base region, and a collector barrier region between the collector region and the base region. At least one of the emitter region, the base region, and the collector region includes a plurality of metal quantum wires.
SPURIOUS JUNCTION PREVENTION VIA IN-SITU ION MILLING
Systems and techniques that facilitate spurious junction prevention via in-situ ion milling are provided. In various embodiments, a method can comprise forming a tunnel barrier of a Josephson junction on a substrate during a shadow evaporation process. In various instances, the method can further comprise etching an exposed portion of the tunnel barrier during the shadow evaporation process. In various embodiments, the shadow evaporation process can comprise patterning a resist stack onto the substrate. In various instances, the etching the exposed portion of the tunnel barrier can leave a protected portion of the tunnel barrier within a shadow of the resist stack. In various instances, the shadow of the resist stack can be based on a direction of the etching the exposed portion of the tunnel barrier. In various embodiments, the shadow evaporation process can further comprise depositing a first superconducting material on the substrate after the patterning the resist stack, oxidizing a surface of the first superconducting material to form the tunnel barrier, and depositing a second superconducting material over the protected portion of the tunnel barrier to form a Josephson junction. In various instances, the etching the exposed portion of the tunnel barrier can occur after the oxidizing the surface of the first superconducting material and before the depositing the second superconducting material.