A novel and useful quantum computing machine architecture that includes a classic computing core as well as a quantum computing core. A programmable pattern generator executes sequences of instructions that control the quantum core. In accordance with the sequences, a pulse generator functions to generate the control signals that are input to the quantum core to perform quantum operations. A partial readout of the quantum state in the quantum core is generated that is subsequently re-injected back into the quantum core to extend decoherence time. Access gates control movement of quantum particles in the quantum core. Errors are corrected from the partial readout before being re-injected back into the quantum core. Internal and external calibration loops calculate error syndromes and calibrate the control pulses input to the quantum core. Control of the quantum core is provided from an external support unit via the pattern generator or can be retrieved from classic memory where sequences of commands for the quantum core are stored a priori in the memory. A cryostat unit functions to provide several temperatures to the quantum machine including a temperature to cool the quantum computing core to approximately 4 Kelvin.

Methods, systems and apparatus for implementing a quantum gate on a quantum system comprising a second qubit coupled to a first qubit and a third qubit. In one aspect, a method includes evolving a state of the quantum system for a predetermined time, wherein during evolving: the ground and first excited state of the second qubit are separated by a first energy gap ω; the first and second excited state of the second qubit are separated by a second energy gap equal to a first multiple of ω minus qubit anharmoniticity−; the ground and first excited state of the first qubit and third qubit are separated by a third energy gap equal to ω−; and the first and second excited state of the first qubit and third qubit are separated by a fourth energy gap equal to the first multiple of the ω minus a second multiple of .

A method for processing a semiconductor device with two closely space gates comprises forming a template structure, wherein the template structure includes at least one sub-structure having a dimension less than the CD. The method further comprises forming a gate layer on and around the template structure. Then, the method comprises removing the part of the gate layer formed on the template structure, and patterning the remaining gate layer into a gate structure including the two gates. Further, the method comprises selectively removing the template structure, wherein the spacing between the two gates is formed by the removed sub-structure.

According to various implementations of the invention, a vertical Josephson Junction device may be realized using molecular beam epitaxy (MBE) growth of YBCO and PBCO epitaxial layers in an a-axis crystal orientation. Various implementations of the invention provide improved vertical JJ devices using SiC or LSGO substrates; GaN, AlN, or MgO buffer layers; YBCO or LSGO template layers; YBCO conductive layers and various combinations of barrier layers that include PBCO, NBCO, and DBCO. Such JJ devices are simple to fabricate with wet and dry etching, and allow for superior current flow across the barrier layers.

A device comprising: a portion of semiconductor; a portion of superconductor arranged to a enable a topological phase having a topological gap to be induced in a region of the semiconductor by proximity effect; and a portion of a non-magnetic material comprising an element with atomic number Z greater than or equal to 26, arranged to increase the topological gap in the topological region of the semiconductor.

Disclosed is a system and a method to use the system that includes a substrate to support a film of liquid helium and an electron subsystem confined by image forces in a direction perpendicular to the surface of the film, a side gate to electrostatically define a boundary of the electron subsystem, a trap gate to electrostatically define an electron trap located outside the boundary of the electron subsystem, and a load gate to selectively open and close access from the electron subsystem to the electron trap, wherein to open access to the electron trap is to apply a first load gate voltage to the load gate to allow the electrons to access the electron trap, and wherein to close access to the electron trap is to apply a second load gate voltage to the load gate to prevent the electrons from accessing the electron trap.

One example includes a superconducting latch system. The system includes a first input stage configured to receive a first input pulse and a second input stage configured to receive a second input pulse. The system also includes a storage loop configured to switch from a first state to a second state in response to receiving the first input pulse, and to switch from the second state to the first state in response to the second input pulse. The first state corresponds to no flux in the storage loop and the second state corresponds to a flux in the storage loop. The system further includes an output stage configured to generate an output pulse in the second state of the storage loop.

Various implementations described herein are related to a device having multiple conductive terminals formed with a superconductive material. The device may include at least one switching layer formed with correlated-electron material (CEM) that is disposed between the multiple conductive terminals. The CEM may comprise carbon or a carbon based compound. The device may refer to a switch structure or similar.

Systems and techniques that facilitate mode-selective couplers for frequency collision reduction are provided. In various embodiments, a device can comprise a control qubit. In various aspects, the device can comprise a first target qubit coupled to the control qubit by a first mode-selective coupler. In various instances, the first mode-selective coupler can facilitate A-mode coupling between the control qubit and the first target qubit. In various embodiments, the device can comprise a second target qubit coupled to the control qubit by a second mode-selective coupler. In various aspects, the second mode selective coupler can facilitate B-mode coupling between the control qubit and the second target qubit. In various embodiments, the first mode-selective coupler can comprise a capacitor that capacitively couples a middle capacitor pad of the control qubit to a middle capacitor pad of the first target qubit. In various embodiments, the second mode-selective coupler can comprise a first capacitor that capacitively couples an end capacitor pad of the control qubit to an end capacitor pad of the first target qubit and can comprise a second capacitor that capacitively couples the end capacitor pad of the control qubit to a middle capacitor pad of the second target qubit.

In an embodiment, a quantum device includes an interposer layer comprising a set of vias. In an embodiment, the quantum device includes a dielectric layer formed on a first side of the interposer, the dielectric layer including a set of transmission lines communicatively coupled to the set of vias. In an embodiment, the quantum device includes a plurality of qubit chips coupled to an opposite side of the interposer layer, each qubit chip of the plurality of qubit chips including: a plurality of qubits on a first side of the qubit chip and a plurality of protrusions on a second side of the qubit chip. In an embodiment, the quantum device includes a heat sink thermally coupled with the plurality of qubit chips, the heat sink comprising a plurality of recesses aligned with the plurality of protrusions of the plurality of qubit chips.