A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.

A method of fabricating a transistor device having a channel of a first conductivity type formed during operation in a body region having a second conductivity type includes forming a first well region of the body region in a semiconductor substrate, performing a first implantation procedure to counter-dope the first well region with dopant of the first conductivity type to define a second well region of the body region, and performing a second implantation procedure to form a source region in the first well region and a drain region in the second well region.

A transistor device includes a transistor implemented over a semiconductor substrate, one or more dielectric layers formed over the transistor, and a handle wafer layer disposed on at least a portion of the one or more dielectric layers, the handle wafer layer including a topside trench defined at least in part by sidewall portions of the handle wafer layer.

The present invention relates to a semiconductor structure and a method for forming the same. The method comprises steps of providing a substrate having a dummy gate, forming a source/drain epitaxy layer doped with deuterium at two sides of the dummy gate on the substrate through a process of chemical vapor deposition for epitaxy; removing the dummy gate and forming a gate structure having a gate oxide layer introducing the deuterium. Because the deuterium is introduced into the gate oxide layer, stable covalent bonds are formed at interface of the gate oxide layer to decrease the number of the dangling bonds. Also, recovery ability of devices when facing hot carrier effect may be improved, and influence of the hot carrier effect on the performance of the devices may be lowered.

The invention provides a body-contact metal-oxide-semiconductor field effect transistor (MOSFET) device. The body-contact MOSFET device includes a substrate. An active region is disposed on the substrate. A gate strip is extended along a first direction disposed on a first portion of the active region. A source doped region and a drain doped region are disposed on a second portion and a third portion of the active region, adjacent to opposite sides of the gate strip. The opposite sides of the gate strip are extended along the first direction. A body-contact doped region is disposed on a fourth portion of the active region. The body-contact doped region is separated from the gate strip by a fifth portion of the active region. The fifth portion is not covered by any silicide features.

A semiconductor device is manufactured by forming an oxide layer, forming an insulating layer and a sacrificial layer over the oxide layer, forming a conductive layer over the insulating layer and the sacrificial layer, and performing heat treatment after the formation of the conductive layer so that a first mixed layer is formed in a region of the oxide layer that is in contact with the conductive layer and a second mixed layer is formed in a region of the sacrificial layer that is in contact with the conductive layer. The first mixed layer includes at least one of elements included in the conductive layer. The second mixed layer includes at least one of elements included in the conductive layer. The resistance value of the first mixed layer is smaller than that of the oxide layer.

A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET. In one embodiment, the accumulated charge control techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.

A display apparatus includes a substrate having a plurality of pixel areas, and a pixel circuit including a storage capacitor and a plurality of thin film transistors (TFTs) which are disposed in each pixel area. At least one of the plurality of TFTs includes a semiconductor layer disposed on the substrate and including a first ion impurity, a source area and a drain area, which are spaced apart from each other, have a first depth from a surface of the semiconductor layer, and include a second ion impurity, a gate electrode disposed on the semiconductor layer between the source area and the drain area, and a bias wiring electrically connected to the semiconductor layer and disposed adjacent to at least one of the source area and the drain area.

A semiconductor device includes a substrate and a fin over the substrate. The fin includes a source region, a drain region, a channel region, and a biasing region. The channel region and the biasing region sandwich one of the source and drain regions. The FinFET further includes a gate over the substrate. The gate engages the fin adjacent to the channel region, thereby forming a field effect transistor (FET). The biasing region is configured to bias the FET when a voltage is applied across the biasing region and the source region.

MOSFET-based IC architectures, including SOI NEDMOS ICs and bulk semiconductor LDMOS ICs, that mitigate or eliminate the problems of edge transistors. One IC embodiment includes end-cap body contact regions angle-implanted to have a first characteristic (e.g., P+), a drift region, and a gate structure partially overlying the end-cap body contact regions and the drift region and including a conductive layer having a third characteristic (e.g., N+) and a first side angle-implanted to have the first characteristic. Steps for fabricating such an IC include implanting a dopant at an angle in the range of about 5 to about 60 within the end-cap body contact regions and within the first side of the conductive layer in a region of the gate structure overlying the end-cap body contact regions, wherein the angle-implanted dopant results in the first characteristic for the end-cap body contact regions and the first side of the conductive layer.