Patent classifications
H10D30/6711
Method and apparatus improving gate oxide reliability by controlling accumulated charge
A method and apparatus are disclosed for use in improving gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit includes a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge. Determinations are made of effects of an uncontrolled accumulated charge and a controlled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the determinations, and the circuit is operated using techniques for ACC operatively coupled to the SOI MOSFET. In one embodiment, the ACC techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.
METHODS RELATED TO TRANSISTORS HAVING SELF-ALIGNED BODY TIE
A transistor can be fabricated by a method that includes forming or providing a first type active region and a second type active region, implementing a source and a drain with the first type active region, forming a body tie with the second type active region, and forming a gate relative to the source and the drain. The method can further include dimensioning either or both of the first and second type active regions to provide a gap between the first and second type active regions on each side of the gate, such that a connecting portion of the body tie engaging the body is substantially covered by the gate.