A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

The present invention provides compositions comprising a metal oxide electrode, a passivating agent on its surface, and a hybrid organic-inorganic perovskite active layer in contact with the metal oxide electrode surface. The presence of a passivating agent on the metal oxide surface increases stability and/or photovoltaic power conversion efficiency of the electronic component comprising a composition of the invention.

A field-effect transistor comprises, on a substrate, a source electrode, a drain electrode, and a gate electrode; a semiconductor layer in contact with the source electrode and the drain electrode; wires individually electrically connected to the source electrode and the drain electrode; and a gate insulating layer that insulates the semiconductor layer from the gate electrode, wherein a connecting portion between the source electrode and the wire forms a continuous phase, and a connecting portion between the drain electrode and the wire forms a continuous phase, the portions constituting the continuous phases contain at least an electrically conductive component and an organic component, and integrated values of optical reflectance at a region of a wavelength of 600 nm or more and 900 nm or less on the wires are higher than integrated values of optical reflectance at a region of a wavelength of 600 nm or more and 900 nm or less on the source electrode and the drain electrode.

Devices comprising a resistance-switching polymer film are described. Also described are methods of making the devices comprising the resistance-switching polymer film.

Described is a flowable preparation for depositing a passivation layer on an organic electronic (OE) device containing an organic layer; the organic layer is selected from an organic semiconductor (OSC) layer and an organic gate insulator (OGI) layer; the preparation comprises a passivating material and a solvent; the solvent includes lactate and/or derivatives thereof. Further described are an OE device and a manufacture method therefor.

A thin film transistor, a manufacturing method of the same, and a CMOS inverter are provided. The thin film transistor includes a base substrate, a dielectric layer, and a semiconductor layer. A first channel is provided between the source and the drain. Carbon nanotubes are provided in the first channel. A second channel is provided between the drain and the gate. An ion gel is provided in the second channel. By regulating a composition of the ion gel and a content of a dopant, a threshold voltage of a carbon nanotube thin film transistor is effectively controlled.

Compositions of matter described as urea (multi)-urethane (meth)acrylate-silanes having the general formula R.sub.A—NH—C(O)—N(R.sup.4)—R.sup.11—[O—C(O)NH—R.sub.S].sub.n, or R.sub.S—NH—C(O)—N(R.sup.4)—R.sup.11—[O—C(O)NH—R.sub.A].sub.n. Also described are articles including a substrate, a base (co)polymer layer on a major surface of the substrate, an oxide layer on the base (co)polymer layer; and a protective (co)polymer layer on the oxide layer, the protective (co)polymer layer including the reaction product of at least one urea (multi)-urethane (meth)acrylate-silane precursor compound. The substrate may be a (co)polymer film or an electronic device such as an organic light emitting device, electrophoretic light emitting device, liquid crystal display, thin film transistor, or combination thereof. Methods of making such urea (multi)-urethane (meth)acrylate-silane precursor compounds, and their use in composite films and electronic devices are also described. Methods of using multilayer composite films as barrier films in articles selected from solid state lighting devices, display devices, and photovoltaic devices are also described.

Provided are P-type semiconductor layer, P-type multilevel element, and manufacturing method for the element. The P-type multilevel element comprises a gate electrode, an active structure overlapping the gate electrode, a gate insulating layer disposed between the gate electrode and the active structure, and source and drain electrodes electrically connected to both ends of the active structure, respectively. The active structure has a first P-type active layer, a second P-type active layer, and a barrier layer disposed between the first P-type active layer and the second P-type active layer. A threshold voltage for forming a channel in the first P-type active layer and a threshold voltage for forming a channel in the second P-type active layer have different values.

Provided are an organic thin film transistor, an organic semiconductor film, a compound, an organic thin film transistor-forming composition, and a method of manufacturing the organic thin film transistor. The organic thin film transistor includes the organic semiconductor film. The organic semiconductor film includes a compound represented by a specific formula. The organic semiconductor film, the compound, and the organic thin film transistor-forming composition can be preferably used in the organic thin film transistor. The method of manufacturing the organic thin film transistor includes a step of forming an organic semiconductor film by applying the organic thin film transistor-forming composition to a substrate.

A technology called RINSE (Removal of Incubated Nanotubes through Selective Exfoliation) is demonstrated. RINSE removes carbon nanotube (CNT) aggregates in CNFETs without compromising CNFET performance. In RINSE, CNTs are deposited on a substrate, coated with a thin adhesive layer, and sonicated. The adhesive layer is strong enough to keep the individual CNTs on the substrate, but not the larger CNT aggregates. When combined with a CNFET CMOS process as disclosed here, record CNFET CMOS yield and uniformity can be realized.