The total silicon area used by a plurality of high voltage transistors in an array of NAND cells is reduced by modifying the silicon area layout such that the size of the source and drain of each of the plurality of high voltage transistors is dependent on the maximum voltage to be applied to each of the source and drain for the respective one of the plurality of high voltage transistors.

According to one embodiment, a semiconductor storage device includes: a substrate; a plurality of first gate electrodes arranged in a first direction intersecting with a substrate surface; a first semiconductor film extending in the first direction and facing the plurality of first gate electrodes; a first gate insulating film provided between the plurality of first gate electrodes and the first semiconductor film; a second gate electrode disposed farther away from the substrate than the plurality of first gate electrodes; a second semiconductor film that extends in the first direction, faces the second gate electrode, and has, in the first direction, one end connected to the first semiconductor film; and a second gate insulating film provided between the second gate electrode and the second semiconductor film. The second gate electrode includes: a first portion; and a second portion provided between the first portion and the second semiconductor film, and facing the second semiconductor film. At least a portion of the second portion is provided closer to a side of the substrate than a surface of the first portion on the side of the substrate side in the first direction.

In a semiconductor device including a plurality of memory regions formed of split-gate type MONOS memories, threshold voltages of memory cells are set to different values for each memory region. Memory cells having different threshold voltages are formed by forming a metal film, which is a work function film constituting a memory gate electrode of a memory cell in a data region, and a metal film, which is a work function film constituting a memory gate electrode of a memory cell in a code region, of different materials or different thicknesses.

Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.

The present disclosure relates to a flash memory structure. The flash memory structure includes a first doped region and a second doped region disposed within a substrate. A select gate is disposed over the substrate between the first doped region and the second doped region. A floating gate is disposed over the substrate between the select gate and the first doped region, and a control gate is over the floating gate. The floating gate extends along multiple surfaces of the substrate.

In a method of manufacturing a non-volatile memory device, insulating layers and conductive gates may be alternately formed on a semiconductor substrate to form a stack structure. A contact hole may be formed through the stack structure. A channel layer may be formed on a surface of the contact hole. The contact hole may be filled with a gap-fill insulating layer. The gap-fill insulating layer may be etched by a target depth to define a preliminary junction region. The channel layer may be etched until a surface of the channel layer may correspond to a surface of an uppermost gate among the gates. Diffusion-preventing ions may be implanted into the channel layer. A capping layer with impurities may be formed in the preliminary junction region.

A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, a gate line structure disposed over the substrate, a gate dielectric layer covering one sidewall surface of the gate line structure and disposed over the substrate, a channel layer disposed to cover the gate dielectric layer and disposed over the substrate, a bit line structure and a resistance change structure to contact different portions of the channel layer over the substrate, and a source line structure disposed in the resistance change structure. The gate line structure includes at least one gate electrode layer pattern and interlayer insulation layer pattern that are alternately stacked along a first direction perpendicular to the substrate, and extends in a second direction perpendicular to the first direction.

A memory device includes a conductive layer, a plurality of first electrode layers, a first semiconductor layer extending through the plurality of first electrode layers in a first direction toward the plurality of first electrode layers from the conductive layer, a first insulating film including a tunneling insulator film, a charge-trapping film and a blocking insulator film, a second electrode layer, and a semiconductor base. The charge-trapping film is spaced along the first direction from the semiconductor base, a distance in the first direction between the charge-trapping film and the semiconductor base is larger than a thickness of the blocking insulator film in a second direction toward the plurality of first electrode layers from the first semiconductor layer.

A three-dimensional semiconductor memory device is disclosed. The device may include a substrate including a cell array region and a connection region provided at an end portion of the cell array region, an electrode structure extending from the cell array region to the connection region, the electrode structure including electrodes sequentially stacked on the substrate, an upper insulating layer provided on the electrode structure, a first horizontal insulating layer provided in the upper insulating layer and extending along the electrodes, and first contact plugs provided on the connection region to penetrate the upper insulating layer and the first horizontal insulating layer. The first horizontal insulating layer may include a material having a better etch-resistive property than the upper insulating layer.

A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a source structure formed on a base, an etch prevention layer formed on the source structure, bit lines, a stack structure located between the etch prevention layer and the bit lines and including conductive layers and insulating layers that are alternately stacked on each other, and a channel structure passing through the stack structure and the etch prevention layer, wherein a lower portion of the channel structure is located in the source structure and a sidewall of the lower portion of the channel structure is in direct contact with the source structure.