A semiconductor device according to an embodiment includes a substrate, first to third conductors, and first and second contacts. The first conductor is provided in a first layer above the substrate. The first contact extends in a first direction, and is provided on the first conductor. The second conductor is provided in the first layer and is insulated from the first conductor. The third conductor is provided between the second conductor and the substrate. The second contact extends in the first direction through the second conductor, and is provided on the third conductor. A width of the second contact, as viewed in a second direction, differs between a portion above a boundary face that is included in the first layer and is parallel to the surface of the substrate, and a portion that is below the boundary face.

In a MONOS memory of the split-gate type formed by a field effect transistor formed on a fin, it is prevented that the rewrite lifetime of the MONOS memory is reduced due to charges being locally transferred into and out of an ONO film in the vicinity of the top of the fin by repeating the write operation and the erase operation. By forming a source region at a position spaced downward from a first upper surface of the fin in a region directly below a memory gate electrode, the current is prevented from flowing concentratedly at the upper end of the fin.

Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.

In a semiconductor device including a plurality of memory regions formed of split-gate type MONOS memories, threshold voltages of memory cells are set to different values for each memory region. Memory cells having different threshold voltages are formed by forming a metal film, which is a work function film constituting a memory gate electrode of a memory cell in a data region, and a metal film, which is a work function film constituting a memory gate electrode of a memory cell in a code region, of different materials or different thicknesses.

According to one embodiment, a semiconductor memory device includes a plurality of electrodes, extending in a first direction and a second direction orthogonal to the first direction are stacked one over the other, and include opposed sides extending in the second direction, a plurality of protrusion portions extending from the first side of the electrodes and spaced from one another in the second direction, and an extraction portion extending from the second side of the electrode. First and second contact plugs extend in a third direction orthogonal to the first and second directions, one of each contacting one of the extraction portions, wherein the extraction portion extending from the uppermost of the electrodes is located closer to the center of the second side in the second direction, than the location of the extraction portion extending from the lowermost of the electrodes.

Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.

A semiconductor device includes first and second select lines, first and second vertical pillars, and first and second subsidiary lines. The select lines are spaced apart and include a first separating insulation layer therebetween. Each of the first and second vertical pillars is connected to a corresponding one of the first or second select lines. The first vertical pillars are closer to the first separating insulation layer. The second vertical pillars arranged in an oblique direction from the first vertical pillars. Each of the first subsidiary lines connects a pair of the first vertical pillars. Each of the second subsidiary lines connects a pair of the second vertical pillars adjacent. The first and second subsidiary lines are alternately disposed along a first direction, and ends of the first and second subsidiary lines are aligned along the first direction.

According to one embodiment, a semiconductor memory device includes a plurality of electrodes, extending in a first direction and a second direction orthogonal to the first direction are stacked one over the other, and include opposed sides extending in the second direction, a plurality of protrusion portions extending from the first side of the electrodes and spaced from one another in the second direction, and an extraction portion extending from the second side of the electrode. First and second contact plugs extend in a third direction orthogonal to the first and second directions, one of each contacting one of the extraction portions, wherein the extraction portion extending from the uppermost of the electrodes is located closer to the center of the second side in the second direction, than the location of the extraction portion extending from the lowermost of the electrodes.

Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.

A three-dimensional memory device includes an alternating stack of insulating layers and word lines located over a front side surface of a semiconductor substrate, memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film, drain regions contacting a respective vertical semiconductor channel, bit lines electrically connected to the respective drain regions, driver circuitry for the memory stack structures located on a backside of the semiconductor substrate, and electrically conductive paths vertically extending through the semiconductor substrate and electrically connecting nodes of the driver circuitry to respective word lines or bit lines.