Some embodiments include an assembly having a memory cell with an active region which includes a body region between a pair of source/drain regions. A charge-storage material is adjacent to the body region. A conductive gate is adjacent to the charge-storage material. A hole-recharge arrangement is configured to replenish holes within the body region during injection of holes from the body region to the charge-storage material. The hole-recharge arrangement includes a heterostructure active region having at least one source/drain region of a different composition than the body region, and/or includes an extension coupling the body region with a hole-reservoir. A wordline is coupled with the conductive gate. A first comparative digit line is coupled with one of the source/drain regions, and a second comparative digit line is coupled with the other of the source/drain regions.

A semiconductor structure includes a first semiconductor die containing a recesses, and a second semiconductor die which is embedded in the recess in the first semiconductor die and is bonded to the first semiconductor die.

A semiconductor device according to an embodiment includes first and second chips, and a first conductor. The first chip includes a first substrate, a first circuit and a first joint metal. The first circuit is provided on the first substrate. The first joint metal is connected to the first circuit. The second chip includes a second substrate, a second circuit, and a second joint metal. The second substrate includes P-type and N-type well regions. The second circuit is provided on the second substrate and includes a first transistor. The second joint metal is connected to the second circuit and the first joint metal. The first conductor is connected to the N-type well region from a top region of the second chip. The P-type well region is arranged between a gate electrode of the first transistor and the N-type well region.

A semiconductor device includes a memory cell formed on a semiconductor substrate. The memory cell includes a first source region and a first drain region that are formed in the semiconductor substrate and a first selection gate, and a first floating gate disposed in series between the first source region and the first drain region. A first floating gate transistor including the first drain region and the first floating gate has a threshold set lower than a threshold of a first selection gate transistor including the first source region and the first selection gate.

A semiconductor memory includes first to fourth stacked bodies. The first stacked body includes a first conductor, and an alternating stack of first insulators and second conductors above the first conductor in a region. The second stacked body includes a third conductor, and an alternating stack of second insulators and fourth conductors above the third conductor in another region. The third stacked body includes a fifth conductor adjacent to the first conductor via a third insulator in a separation region. The fourth stacked body includes a seventh conductor adjacent to the third conductor via a fifth insulator in the separation region. The fifth conductor is electrically insulated from the seventh conductor.

Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

According to one embodiment, a semiconductor storage device includes: a substrate; a plurality of first gate electrodes arranged in a first direction intersecting with a substrate surface; a first semiconductor film extending in the first direction and facing the plurality of first gate electrodes; a first gate insulating film provided between the plurality of first gate electrodes and the first semiconductor film; a second gate electrode disposed farther away from the substrate than the plurality of first gate electrodes; a second semiconductor film that extends in the first direction, faces the second gate electrode, and has, in the first direction, one end connected to the first semiconductor film; and a second gate insulating film provided between the second gate electrode and the second semiconductor film. The second gate electrode includes: a first portion; and a second portion provided between the first portion and the second semiconductor film, and facing the second semiconductor film. At least a portion of the second portion is provided closer to a side of the substrate than a surface of the first portion on the side of the substrate side in the first direction.

A semiconductor memory includes first to fourth stacked bodies. The first stacked body includes a first conductor, and an alternating stack of first insulators and second conductors above the first conductor in a region. The second stacked body includes a third conductor, and an alternating stack of second insulators and fourth conductors above the third conductor in another region. The third stacked body includes a fifth conductor adjacent to the first conductor via a third insulator in a separation region. The fourth stacked body includes a seventh conductor adjacent to the third conductor via a fifth insulator in the separation region. The fifth conductor is electrically insulated from the seventh conductor.

Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.