A memory device with a three-dimensional (3D) staircase memory stack includes dummy connectors proximate semi-isolated connectors. The memory device includes multiple wordlines stacked in a 3D staircase stack, which includes a wordline at an edge of a region of the staircase. The memory device includes vertical connectors through an isolation layer on the 3D staircase stack to connect the wordlines with conductive lines in an access layer. A wordline at the edge of the region of the staircase has a vertical connector that will be adjacent a connector on one side and not on the other side. The memory device includes at least one dummy vertical connector on the edge side of the vertical connector of the wordline on the edge, wherein the dummy vertical connector does not electrically connect a wordline of the 3D staircase stack to a conductive line in the access layer.

A three-dimensional (3D) memory device includes a doped semiconductor layer, a stack structure, a channel structure, and a semiconductor structure. The stack structure includes a plurality of word lines and a select gate line formed on the doped semiconductor layer. The channel structure extends through the plurality of word lines along a first direction and in contact with the doped semiconductor layer. The semiconductor structure extends through the select gate line along the first direction and in contact with the channel structure. The select gate line extends along a second direction perpendicular to the first direction, and the drain select gate line around the semiconductor structure is insulated from the drain select gate line around an adjacent semiconductor structure. A width of the semiconductor structure is less than a width of the channel structure.

A semiconductor device includes a substrate; a first stack structure including first gate electrodes on the substrate; and a second stack structure on the first stack structure; wherein the first stack structure includes a first lower staircase region, a second lower staircase region, and a third lower staircase region, wherein the second stack structure includes a first upper staircase region, a second upper staircase region, a third upper staircase region, and at least one through portion penetrating the second stack structure and on the first to third lower staircase regions, wherein the first lower staircase region has a same shape as a shape of the first upper staircase region, the second lower staircase region has a same shape as a shape of the second upper staircase region, and the third lower staircase region has a same shape as a shape of the third upper staircase region.

A vertical repetition of multiple instances of a unit layer stack is formed over a substrate. The unit layer stack includes an insulating layer and a sacrificial material layer. Lateral recesses are formed by removing the sacrificial material layers selective to the insulating layers. Each lateral recess is sequentially fill with at least one conductive fill material and an insulating fill material, and vertically-extending portions of the at least one conductive fill material are removed such that a vertical layer stack including a first-type electrically conductive layer, a seamed insulating layer, and a second-type electrically conductive layer are formed in each lateral recess. Memory opening fill structures including a respective vertical stack of memory elements is formed through the insulating layers and the layer stacks. Access points for providing an etchant for removing the sacrificial material layers may be provided by memory openings, contact via cavities or backside trenches.

A vertical repetition of multiple instances of a unit layer stack is formed over a substrate. The unit layer stack includes an insulating layer and a sacrificial material layer. Lateral recesses are formed by removing the sacrificial material layers selective to the insulating layers. Each lateral recess is sequentially fill with at least one conductive fill material and an insulating fill material, and vertically-extending portions of the at least one conductive fill material are removed such that a vertical layer stack including a first-type electrically conductive layer, a seamed insulating layer, and a second-type electrically conductive layer are formed in each lateral recess. Memory opening fill structures including a respective vertical stack of memory elements is formed through the insulating layers and the layer stacks. Access points for providing an etchant for removing the sacrificial material layers may be provided by memory openings, contact via cavities or backside trenches.

A non-volatile memory device, includes a source region and a drain region disposed in a channel length direction on a substrate; a flash cell, including a floating gate and a control gate, disposed between the source region and the drain region; a selection gate disposed between the source region and the flash cell; a selection line connecting the selection gate; a word line connecting the control gate; a common source line connected to the source region; and a bit line connected to the drain region.

A semiconductor device and a data storage system, the device including a lower structure; and an upper structure on the lower structure and including a memory cell array, wherein the lower structure includes a semiconductor substrate, first and second active regions spaced apart from each other in a first direction on the semiconductor substrate, the first and second active regions being defined by an isolation insulating layer on the semiconductor substrate, and first and second gate pattern structures extending in the first direction to cross the first and second active regions, respectively, on the semiconductor substrate, the first gate pattern structure and the second gate pattern structure have first and second end portions spaced apart from each other in a facing manner in the first direction, respectively, and the first and second end portions are concavely curved in opposite directions away from each other in a plan view.

A semiconductor device includes a stacked film including a plurality of electrode layers and a plurality of insulating layers alternately stacked in a first direction and a columnar portion including a charge storage layer and a first semiconductor layer and extending in the first direction in the stacked film. The device further includes a second semiconductor layer provided on the stacked film and the columnar portion, and at least a part of regions in the second semiconductor layer contains phosphorus having an atomic concentration of 1.0×10.sup.21/cm.sup.3 or more and hydrogen having an atomic concentration of 1.0×10.sup.19/cm.sup.3 or less.

Disclosed is a three-dimensional semiconductor memory device including a carbon-containing layer on a substrate, a plurality of electrode interlayer dielectric layers and a plurality of electrode layers that are alternately stacked on the carbon-containing layer, a cell vertical pattern that penetrates at least some of the electrode interlayer dielectric layers and the electrode layers, and a semiconductor pattern between the cell vertical pattern and the carbon-containing layer. The substrate includes a plurality of first grains. The semiconductor pattern includes a plurality of second grains. An average size of the second grains is less than an average size of the first grains.

A novel semiconductor device is provided. A structure body extending in a first direction, a first conductor extending in a second direction, and a second conductor extending in the second direction are provided. In a first intersection portion where the structure body and the first conductor intersect with each other, a first insulator, a first semiconductor, a second insulator, a second semiconductor, a third insulator, a fourth insulator, and a fifth insulator are provided concentrically around a third conductor. In a second intersection portion where the structure body and the second conductor intersect with each other, the first insulator, the first semiconductor, the second insulator, a fourth conductor, the second semiconductor, and the third insulator are provided concentrically around the third conductor.