Embodiments of an etching method for a material layer of a NAND memory device are disclosed. An example method of chemically etching a material layer on one or more substrates includes mixing an etchant solution within a bath and allowing the etchant solution to reach a quiescent state. After the etchant solution has reached the quiescent state, the method includes loading the one or more substrates into the bath. The one or more substrates includes a plurality of openings having the material layer disposed on an inside surface of the plurality of openings. The method also includes allowing the one or more substrates to remain in the bath for a predetermined time period, such that a thickness of the material layer is reduced by the etchant solution.

Some embodiments include a method of forming integrated circuitry. A structure has first conductive lines over a dielectric bonding region, has semiconductor material pillars extending upwardly from the first conductive lines, and has second conductive lines over the first conductive lines and extending along sidewalls of the semiconductor material pillars. The first conductive lines extend along a first direction, and the second conductive lines extend along a second direction which intersects the first direction. The structure includes semiconductor material under the dielectric bonding region. Memory structures are formed over the semiconductor material pillars. The memory structures are within a memory array. Third conductive lines are formed over the memory structures. The third conductive lines extend along the first direction. Individual memory structures of the memory array are uniquely addressed through combinations of the first, second and third conductive lines.

Present disclosure provides a semiconductor structure including a first transistor and a second transistor. The first transistor includes a semiconductor substrate having a top surface and a first anti-punch through region doped with a first conductivity dopant at the top surface. The first transistor further includes a first channel over the top surface of the semiconductor substrate by a first distance. The second transistor includes a second anti-punch through region doped with a second conductivity dopant at the top surface of the semiconductor substrate. The second transistor further includes a second channel over the top surface of the semiconductor substrate by a second distance greater than the first distance. Present disclosure also provides a method for manufacturing the semiconductor structure described herein.

Some embodiments include a method of forming integrated circuitry. A structure has first conductive lines over a dielectric bonding region, has semiconductor material pillars extending upwardly from the first conductive lines, and has second conductive lines over the first conductive lines and extending along sidewalls of the semiconductor material pillars. The first conductive lines extend along a first direction, and the second conductive lines extend along a second direction which intersects the first direction. The structure includes semiconductor material under the dielectric bonding region. Memory structures are formed over the semiconductor material pillars. The memory structures are within a memory array. Third conductive lines are formed over the memory structures. The third conductive lines extend along the first direction. Individual memory structures of the memory array are uniquely addressed through combinations of the first, second and third conductive lines.

Tunneling field-effect transistors (TFETs) and associated methods of fabrication are disclosed herein. An exemplary TFET includes a protrusion that extends vertically from a substrate. A drain region is in a bottommost portion of the protrusion. A source region is in a topmost portion of the protrusion. A gate stack that wraps a middle portion of the protrusion. The gate stack further wraps around a portion of the source region and a portion of the drain region. Spacers are along a portion of the topmost portion of the protrusion. The TFET further includes a drain contact coupled to the drain region, a gate contact coupled to the gate stack, and a source contact coupled to the source region. The source contact has a width that is greater than a width of the source region. The source contact is disposed on the source region and a portion of the spacers.

A triac has a vertical structure formed from a silicon substrate having an upper surface side. A main metallization on the upper surface side has a first portion resting on a first region of a first conductivity type formed in a layer of a second conductivity type. A second portion of the main metallization rests on a portion of the layer. A gate metallization on the upper surface side rests on a second region of the first conductivity type formed in the layer in the vicinity of the first region. A porous silicon bar formed in the layer at the upper surface side has a first end in contact with the gate metallization and a second end in contact with the main metallization.

A method for manufacturing a semiconductor device includes forming a first semiconductor layer having a first concentration of germanium on a semiconductor substrate, a second semiconductor layer having a second concentration of germanium on the first semiconductor layer, and a third semiconductor layer having a third concentration of germanium on the second semiconductor layer. The method also includes patterning the first, second and third semiconductor layers into at least one fin, and reducing a width of the second semiconductor layer of the at least one fin. In the method, a bottom source/drain region is grown from the substrate adjacent a base portion of the at least one fin, a gate structure is formed on and around the second semiconductor layer, and a top source/drain region is grown from the third semiconductor layer.

A method for fabricating a high-voltage insulated gate type bipolar semiconductor device by comparing to a reference structure of the same includes determining a width S of a mesa region in which the gate insulating film and the MOS transistor are formed, and a trench depth D.sub.T, based on a scaling ratio K, in comparison with a second width and a second trench depth of the reference structure, and setting a cell width 2W of the high-voltage insulated gate type bipolar semiconductor device to be equal in length to a second length of the reference structure, the scaling ratio K being defined as K=Y/X, where X indicates a size of a target portion to be miniaturized in the high-voltage insulated gate type bipolar semiconductor device, and Y indicates a size of a target portion to be miniaturized in the reference structure.

A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, an active cell field in the body, and a plurality of first and second cells in the active cell field. Each cell is electrically connected to the first load terminal structure and to a drift region. Each first cell includes a mesa having a port region electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each second cell includes a mesa having a port region of the opposite conductivity type electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each mesa is spatially confined in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure and has a total extension of less than 100 nm in the direction.

A semiconductor device includes a first bidirectional diode of a ring shape surrounding a central region and including a first connection section and a second connection section which is provided to the inner side of the ring shape from the first connection section, a semiconductor element in the central region including a first semiconductor element electrode, a second semiconductor element electrode, and a control electrode, the first semiconductor element electrode electrically connected to the first connection section and the second semiconductor element electrode electrically connected to the control electrode, a first resistor including a first resistor electrode and a second resistor electrode, the first resistor electrode electrically connected to the second connection section and the control electrode, a second bidirectional diode electrically connected to the second resistor electrode and to the second semiconductor element electrode, and a second resistor element electrically connected to the second resistor electrode.