A semiconductor memory device includes a stack disposed over a first substrate; an etch barrier including a plurality of dummy channels which pass through the stack and surround a coupling region; and a plurality of channels passing through the stack in a cell region outside the coupling region. The stack has a structure in which first dielectric layers and second dielectric layers are alternately stacked, inside the coupling region, and has a structure in which the first dielectric layers and electrode layers are alternately stacked, outside the coupling region.

Provided is a non-volatile memory including a conductor layer, a memory device, and a selector. The selector is located between and electrically connected to the memory device and the conductive layer. The selector includes a metal filling layer, a barrier layer, and a rectify layer. The metal filling layer is electrically connected to the memory device. The barrier layer is located on the sidewall and the bottom surface of the metal filling layer. The rectify layer is wrapped around the barrier layer. The rectify layer includes a first portion and a second portion. The first portion is located between the barrier layer on the bottom surface of the metal filling layer and the conductive layer. The second portion and the metal filling layer sandwich the barrier layer on the sidewall of the metal filling layer. The first portion has more diffusion paths of metal ions than the second portion.

A process for fabricating an integrated circuit includes the fabrication of a first transistor and a floating-gate transistor. The fabrication process for the first transistor and the floating-gate transistor utilizes a common step of forming a dielectric layer. This dielectric layer is configured to form a tunnel-dielectric layer of the floating-gate transistor (which allows transfer of charge via the Fowler-Nordheim effect) and to form a gate-dielectric layer of the first transistor.

A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening through the alternating stack, forming lateral recesses at levels of the sacrificial material layers around the memory opening, forming a vertical stack of discrete clam-shaped semiconductor liners in the lateral recesses, replacing the vertical stack of discrete clam-shaped semiconductor liners with a vertical stack of inner clam-shaped metallic liners, forming a vertical stack of discrete charge storage elements on the vertical sack of inner clam-shaped metallic liners, forming a tunneling dielectric layer and a vertical semiconductor channel over the vertical stack of discrete charge storage elements and the vertical stack of inner clam-shaped metallic liners, and replacing each of the sacrificial material layers with an electrically conductive layer.

A semiconductor device that can be downsized more than ever before is provided. A semiconductor device 10 includes: an insulating layer 21 provided on an upper side of a substrate 20; a conductor 110 provided within the insulating layer 21; a conductor 120 provided within the insulating layer 21 and facing the conductor 110 in a first direction parallel with a surface of the substrate 20; and an insulating film 130 provided between the conductor 110 and the conductor 120. A thickness of the insulating film 130 in the first direction is smaller than both of a thickness of the conductor 110 in the first direction and a thickness of the conductor 120 in the first direction. A relative permittivity of the insulating film 130 is higher than a relative permittivity of the insulating layer 21. The conductor 110 and the conductor 120 extend in a second direction intersecting the first direction and parallel with the substrate 20.

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and a memory stack structure vertically extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel and a memory film. The vertical semiconductor channel can include a III-V compound semiconductor channel material. A III-V compound substrate semiconductor layer or a III-V compound semiconductor source region can be used to provide low-resistance electrical connection to a bottom end of the vertical semiconductor channel, and a drain region including a graded III-V compound semiconductor material can be used to provide low-resistance electrical connection to a top end of the vertical semiconductor channel.

A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a first single crystalline semiconductor layer, and memory stack structures extending through the alternating stack and containing respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die includes a peripheral circuitry.

A memory structure and its manufacturing method are provided. The memory structure includes a substrate, a tunnel dielectric layer on the substrate and a floating gate on the tunnel dielectric layer. The substrate has a source region and a drain region, and the source region and the drain region are formed on two opposite sides of the floating gate. The memory structure also includes an inter-gate dielectric layer on the floating gate and a control gate on the inter-gate dielectric layer. The memory structure further includes a doping region buried in the floating gate, wherein a sidewall of the doping region is exposed at a sidewall of the floating gate. Also, the doping region and the inter-gate dielectric layer are separated from each other.

A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening through the alternating stack, forming lateral recesses at levels of the sacrificial material layers around the memory opening, forming a vertical stack of discrete clam-shaped semiconductor liners in the lateral recesses, replacing the vertical stack of discrete clam-shaped semiconductor liners with a vertical stack of inner clam-shaped metallic liners, forming a vertical stack of discrete charge storage elements on the vertical sack of inner clam-shaped metallic liners, forming a tunneling dielectric layer and a vertical semiconductor channel over the vertical stack of discrete charge storage elements and the vertical stack of inner clam-shaped metallic liners, and replacing each of the sacrificial material layers with an electrically conductive layer.

A memory device includes an alternating stack of insulating layers, dielectric barrier liners and electrically conductive layers located over a substrate and a memory stack structure extending through each layer in the alternating stack. Each of the dielectric barrier liners is located between vertically neighboring pairs of an insulating layer and an electrically conductive layer within the alternating stack. The memory stack structure includes a memory film and a vertical semiconductor channel, the memory film includes a tunneling dielectric layer and a vertical stack of discrete memory-level structures that are vertically spaced from each other without direct contact between them, and each of the discrete memory-level structures includes a lateral stack including, from one side to another, a charge storage material portion, a silicon oxide blocking dielectric portion, and a dielectric metal oxide blocking dielectric portion.