An integrated circuit contains a flash cell in which the top gate of the sense transistor is a metal sense gate over the floating gate. The source/drain regions of the sense transistor extend under the floating gate so that the source region is separated from the drain region by a sense channel length less than 200 nanometers. The floating gate is at least 400 nanometers wide, so the source/drain regions of the sense transistor extend under the floating gate at least 100 nanometers on each side. The integrated circuit is formed by forming the sense transistor source and drain regions before forming the floating gate.

A method for manufacturing a semiconductor device includes providing a semiconductor substrate having a core region and a peripheral region, and prior to forming a metal silicide in the core region, forming a sidewall layer on opposite sides of a gate structure of a core region device. The sidewall layer includes sequentially, from the inside out, a silicon oxide layer, a first silicon nitride layer, a first silicon nitride layer, a second silicon oxide layer, and a second silicon nitride layer, or the sidewall layer includes, from inside out, a first silicon nitride layer and a second silicon nitride layer. The sidewall layer having such structure ensures that the formed metal silicide has a good morphology in the core region to achieve good device performance.

A method for forming flash memory units is provided. After a logic gate in a select gate PMOS transistor area is separated from a logic gate in a control gate PMOS transistor area, P-type impurities implanted into the logic gate in the select gate PMOS transistor area are diffused into an N-type floating gate polysilicon layer to convert the N-type floating gate into a P-type floating gate by a subsequent high temperature heating process, so that it is possible to successfully form a select gate PMOS transistor having a small surface channel threshold value in a 55 nm process flash memory unit, and achieve mass production. Further, a two-step growth process of the logic gate and a process for separating the logic gate can form a surface channel of the select gate PMOS transistor having a smaller threshold value without affecting the floating gate doping of the control gate PMOS transistor.

Conductive channel technology is disclosed. In one example, a memory component can include a source line, a conductive channel having first and second conductive layers electrically coupled to the source line and memory cells adjacent to the conductive channel. In one aspect, channel conductivity and reliability is improved over a single layer conductive channel formation scheme by preventing unwanted oxide formation, increasing the interface contact area, and by modulating material grain size and boundaries via multiple thin channel integration scheme. Associated systems and methods are also disclosed.

A method for forming flash memory units is provided. After a logic gate in a select gate PMOS transistor area is separated from a logic gate in a control gate PMOS transistor area, P-type impurities implanted into the logic gate in the select gate PMOS transistor area are diffused into an N-type floating gate polysilicon layer to convert the N-type floating gate into a P-type floating gate by a subsequent high temperature heating process, so that it is possible to successfully form a select gate PMOS transistor having a small surface channel threshold value in a 55 nm process flash memory unit, and achieve mass production. Further, a two-step growth process of the logic gate and a process for separating the logic gate can form a surface channel of the select gate PMOS transistor having a smaller threshold value without affecting the floating gate doping of the control gate PMOS transistor.

A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.

A method of manufacturing a flash memory cell is provided including forming a plurality of semiconductor fins on a semiconductor substrate, forming floating gates for a sub-set of the plurality of semiconductor fins and forming a first insulating layer between the plurality of semiconductor fins. The first insulating layer is recessed to a height less than the height of the plurality of semiconductor fins and sacrificial gates are formed over the sub-set of the plurality of semiconductor fins. A second insulating layer is formed between the sacrificial gates and, after that, the sacrificial gates are removed. Recesses are formed in the first insulating layer and sense gates and control gates are formed in the recesses for the sub-set of the plurality of semiconductor fins. The first and second insulating layers may be oxide layers.

A method for manufacturing a semiconductor device includes providing a substrate, a first conductor, a second conductor, a first dielectric, a second dielectric, and a designated region. The first conductor is positioned between the first dielectric and the substrate. The second conductor is positioned between the second dielectric and the substrate. The first designated region is positioned in the substrate. The method includes providing a conductive material layer, which completely covers the first dielectric and the second dielectric. The method includes partially removing the conductive material layer to form a third conductor and a fourth conductor. The first dielectric is positioned between the third conductor and the first conductor. The fourth conductor directly contacts the designated region. The method includes implementing a memory unit using the first conductor and the third conductor and includes implementing a logic unit using the second conductor and the designated region.

A semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor includes a first source terminal formed of a material and connected to a first source, a first drain terminal formed of the material and connected to a first drain, a first gate overlapping a portion of the substrate that is between the first source and the first drain, and a first dielectric layer between the first gate and the substrate. The second transistor includes a control gate formed of the material and overlapping a part of the substrate that is positioned between a second source and a second drain, a second dielectric layer between the control gate and the substrate, a floating gate extending through the second dielectric layer to contact a doped region in the substrate, and an insulating member positioned between the control gate and the floating gate.

A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.