Semiconductor structures and methods for forming those semiconductor structures are disclosed. For example, a p-type or n-type semiconductor structure is disclosed. The semiconductor structure has a polar crystal structure with a growth axis that is substantially parallel to a spontaneous polarization axis of the polar crystal structure. The semiconductor structure changes in composition from a wider band gap (WBG) material to a narrower band gap (NBG) material or from a NBG material to a WBG material along the growth axis to induce p-type or n-type conductivity.

A manufacturing method of a light-emitting device comprising a first light semiconductor stack and a second semiconductor stack on thereof comprises steps of: providing a substrate with a top surface; forming a semiconductor stack on the substrate; forming a trench in the semiconductor stack to define multiple second semiconductor stacks and expose a first upper surface; forming a scribing region in the first upper surface to define multiple first semiconductor stacks; etching the scribing region to form a first side wall of each of the first semiconductor stack; and dividing the substrate along the scribing region to form multiple light-emitting devices, wherein the first side wall and the top surface form an acute angle between thereof, and 3080, and a side surface of the substrate directly connects the top surface after the dividing step.

The electronic device comprises a substrate (1), at least one semiconductor nanowire (2) and a buffer layer (3) interposed between the substrate (1) and said nanowire (2). The buffer layer (3) is at least partly formed by a transition metal nitride layer (9) from which extends the nanowire (2), said transition metal nitride being chosen from: vanadium nitride, chromium nitride, zirconium nitride, niobium nitride, molybdenum nitride, hafnium nitride or tantalum nitride.

A group-III nitride structure includes a substrate 102 and a fine wall-shaped structure 110 disposed to stand on the substrate 102 in a vertical direction relative to a surface of the substrate 102 and extending in an in-plane direction of the substrate 102. The fine wall-shaped structure 110 contains a group-III nitride semiconductor crystal, and h is larger than d assuming that the height of the fine wall-shaped structure 110 is h and the width of the fine wall-shaped structure 110 in a direction perpendicular to the height direction and the extending direction is d.

The invention provides an optoelectronic device adapted to emit ultraviolet light, including an aluminum nitride single crystalline substrate, wherein the dislocation density of the substrate is less than about 10.sup.5 cm.sup.2 and the Full Width Half Maximum (FWHM) of the double axis rocking curve for the (002) and (102) crystallographic planes is less than about 200 arcsec; and an ultraviolet light-emitting diode structure overlying the aluminum nitride single crystalline substrate, the diode structure including a first electrode electrically connected to an n-type semiconductor layer and a second electrode electrically connected to a p-type semiconductor layer. In certain embodiments, the optoelectronic devices of the invention exhibit a reverse leakage current less than about 10.sup.5 A/cm.sup.2 at 10 V and/or an L80 of at least about 5000 hours at an injection current density of 28 A/cm.sup.2.

An LED element is provided with: a first semiconductor layer formed of an n-type nitride semiconductor; a second semiconductor layer formed on top of the first semiconductor layer and formed of quaternary mixed crystals of Al.sub.x1Ga.sub.y1In.sub.z1N (0<x1<1, 0<y1<1, 0<z1<1 and x1+y1+z1=1); a heterostructure formed on top of the second semiconductor layer and constituted of a laminate structure of a third semiconductor layer formed of In.sub.x2Ga.sub.1-x2N (0<x2<1) having a film thickness of greater than or equal to 10 nm, and a fourth semiconductor layer formed of Al.sub.x3Ga.sub.y3In.sub.z3N (0<x3<1, 0<y3<1, 0z3<1 and x3+y3+z3=1); and a fifth semiconductor layer formed on top of the heterostructure and formed of a p-type nitride semiconductor.

Provided is a display device comprising a substrate; a plurality of transistors disposed on the substrate; a first pixel electrode, a second pixel electrode, and a third pixel electrode respectively connected to the transistors; a first emission layer disposed to overlap the first pixel electrode, a second emission layer disposed to overlap the second pixel electrode, and a third emission layer disposed to overlap the third pixel electrode; and a common electrode disposed on the first emission layer, the second emission layer, and the third emission layer, wherein the first pixel electrode includes a first layer, and a second layer disposed on the first layer and including a Ga-doped ITO.

Provided is a display device comprising a substrate; a plurality of transistors disposed on the substrate; a first pixel electrode, a second pixel electrode, and a third pixel electrode respectively connected to the transistors; a first emission layer disposed to overlap the first pixel electrode, a second emission layer disposed to overlap the second pixel electrode, and a third emission layer disposed to overlap the third pixel electrode; and a common electrode disposed on the first emission layer, the second emission layer, and the third emission layer, wherein the first pixel electrode includes a first layer, and a second layer disposed on the first layer and including a Ga-doped ITO.

The disclosure describes the use of strain to enhance the properties of p- and n-materials so as to improve the performance of III-N electronic and optoelectronic devices. In one example, transistor devices include a channel aligned along uniaxially strained or relaxed directions of the III-nitride material in the channel. Strain is introduced using buffer layers or source and drain regions of different composition

A transistor can include a substrate, an epitaxial oxide layer on the substrate, and a gate layer. The substrate can include a first crystalline material. The epitaxial oxide layer can include a second oxide material including: Li and one of Ni, Al, Ga, Mg, Zn and Ge; or Ni and one of Li, Al, Ga, Mg, Zn and Ge; or Mg and one of Ni, Al, Ga, and Ge; or Zn and one of Ni, Al, Ga, and Ge. The gate layer can include a third oxide material. A bandgap of the third oxide material of the gate can be wider than a bandgap of the second oxide material of the epitaxial oxide layer. The transistor can also include a source electrical contact coupled to the epitaxial oxide layer, a drain electrical contact coupled to the epitaxial oxide layer, and a first gate electrical contact coupled to the gate layer.