A quantum nano-tip (QNT) thin film, such as a silicon nano-tip (SiNT) thin film, for flash memory cells is provided to increase erase speed. The QNT thin film includes a first dielectric layer and a second dielectric layer arranged over the first dielectric layer. Further, the QNT thin film includes QNTs arranged over the first dielectric layer and extending into the second dielectric layer. A ratio of height to width of the QNTs is greater than 50 percent. A QNT based flash memory cell and a method for manufacture a SiNT based flash memory cell are also provided.

Memory devices and methods for forming the same are disclosed. In one embodiment, the device includes a non-volatile memory (NVM) transistor formed in a first region of a substrate, the NVM transistor comprising a channel and a gate stack on the substrate overlying the channel. The gate stack includes a dielectric layer on the substrate, a charge-trapping layer on the dielectric layer, an oxide layer overlying the charge-trapping layer, a first gate overlying the oxide layer, and a first silicide region overlying the first gate. The device includes a metal-oxide-semiconductor transistor formed in a second region of the substrate comprising a gate oxide overlying the substrate in the second region, a second gate overlying the gate oxide, and a second silicide region overlying the second gate. A strain inducing structure overlies at least the NVM transistor and a surface of the substrate in the first region of the substrate.

A memory device has first and second memory cells in and over a substrate. A first doped region is in a first active region. A top surface of the first active region is substantially coplanar with a top surface of the first doped region. A control gate is over the first doped region and extends over a first side of the first doped region and over a second side of the first doped region. A charge storage layer is between the first control gate and the first active region including between the first select gate and the first doped region. A first select gate is over the first active region on the first side of the first doped region and adjacent to the control gate. A second select gate is over the first active region on the second side of the first doped region and adjacent to the control gate.

Provided are a weighting device that may be driven at a low voltage and is capable of embodying multi-level weights, a neural network, and a method of operating the weighting device. The weighting device includes a switching layer that may switch between a high resistance state and a low resistance state based on a voltage applied thereto and a charge trap material layer that traps or discharges charges according to a resistance state of the switching layer. The weighting device may be used for controlling a weight in a neural network.

A semiconductor device includes a substrate, a ferroelectric layer disposed on the substrate, a gate insulation layer disposed on the ferroelectric layer, metal particles disposed in the gate insulation layer, and a gate electrode layer disposed on the gate insulation layer.

Memories, systems, and methods for forming memory cells are disclosed. One such memory cell includes a charge storage node that includes nanodots over a tunnel dielectric and a protective film over the nanodots. In another memory cell, the charge storage node includes nanodots that include a ruthenium alloy. Memory cells can include an inter-gate dielectric over the protective film or ruthenium alloy nanodots and a control gate over the inter-gate dielectric. The protective film and ruthenium alloy can be configured to protect at least some of the nanodots from vaporizing during formation of the inter-gate dielectric.

The present disclosure relates to a split gate memory device. In some embodiments, the split gate memory device includes a memory gate arranged over a substrate, and a select gate arranged over the substrate. An inter-gate dielectric layer is arranged between sidewalls of the memory gate and the select gate that face one another. The inter-gate dielectric layer extends under the memory gate. A first dielectric is disposed above the inter-gate dielectric layer and is arranged between the sidewalls of the memory gate and the select gate.

Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

A dielectric layer is formed over the substrate in the capacitor region and the memory region and a select gate layer is formed over the dielectric layer. A select gate is formed over the memory region and a plurality of lines of electrodes over the capacitor region from the select gate layer. A charge storage layer is formed over the capacitor region and the memory region including over the select gate and the plurality of lines. A control gate layer is formed over the charge storage layer over the capacitor region and over the memory region. The control gate layer is patterned to form a control gate of a memory cell over the memory region and a first electrode of a capacitor over the capacitor region. The plurality of lines are connected to the capacitor region to form a second electrode of the capacitor.

In an embodiment, a semiconductor device includes a High Electron Mobility Transistor (HEMT) including a floating gate. The floating gate includes two or more electrically separated floating gate segments.