A vertical NAND flash memory device and a method of manufacturing the same are provided. The vertical NAND flash memory device includes a charge trap layer arranged on an inner wall of a channel hole vertically formed on a substrate. The charge trap layer includes nanostructures distributed in a base. The nanostructures may include a material having a trap density of about 110.sup.19 cm.sup.3 to about 1010.sup.19 cm.sup.3, and the base may include a material having a conduction band offset (CBO) of about 0.5 eV to about 3.5 eV with respect to the material included in the nanostructures.

The present disclosure relates to a memory device that includes a substrate and source and drain regions formed in the substrate. The memory device includes a gate dielectric formed on the substrate and between the source and drain regions. The memory device also includes a gate structure formed on the gate dielectric and the gate structure has a planar top surface. The memory device further includes a multi-spacer structure that includes first, second, and third spacers. The first spacer is formed on a sidewall of the gate structure and a top surface of one of the source and drain regions. The second spacer is formed on a sidewall of the first spacer and the second spacer has a dielectric constant greater than a dielectric constant of the first spacer. The third spacer is formed on a sidewall of the second spacer and a horizontal surface of the first spacer.

A semiconductor memory device and a method of manufacturing the semiconductor memory device are provided. The semiconductor memory device includes a cell pillar structure and a conductive layer surrounding the external surface of the cell pillar structure. Portions of the external surface of the cell pillar structure are arranged at different distances from a center point on a plurality of first axes and a plurality of second axes radially extending from the center point. The plurality of first axes and the plurality of second axes are alternately arranged in a clockwise direction, and the cell pillar structure includes a plurality of channel portions and an isolation structure extending between the plurality of channel portions from the center point.