A device comprising: a portion of semiconductor; a portion of superconductor arranged to a enable a topological phase having a topological gap to be induced in a region of the semiconductor by proximity effect; and a portion of a non-magnetic material comprising an element with atomic number Z greater than or equal to 26, arranged to increase the topological gap in the topological region of the semiconductor.

A qubit coupling device includes: a dielectric substrate including a trench; a first superconductor layer on a surface of the dielectric substrate where an edge of the first superconductor layer extends along a first direction and at least a portion of the superconductor layer is in contact with the surface of the dielectric substrate, and where the superconductor layer is formed from a superconductor material exhibiting superconductor properties at or below a corresponding critical temperature; a length of the trench within the dielectric substrate is adjacent to and extends along an edge of the first superconductor layer in the first direction, and where the electric permittivity of the trench is less than the electric permittivity of the dielectric substrate.

A system includes a plurality of superconducting wires connected in parallel with one another. The plurality of superconducting wires includes a first superconducting wire and a second superconducting wire. The plurality of superconducting wires are configured to, while receiving a bias current provided to the parallel combination of the plurality of superconducting wires, operate in a superconducting state in the absence of a trigger current. The first superconducting wire is configured to, while receiving the bias current, transition to a non-superconducting state in response to receiving the trigger current. The second superconducting wire is configured to, while receiving the bias current, transition to a non-superconducting state in response to the first superconducting wire transitioning to the non-superconducting state.

Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

A superconducting circuit includes a first component having a first connection point. The first connection point has a first width. The superconducting circuit includes a second component having a second connection point. The second connection point has a second width that is larger than the first width. The superconducting circuit includes a superconducting connector shaped to reduce current crowding. The superconducting connector electrically connects the first connection point and the second connection point. The superconducting connector includes a first taper positioned adjacent the first connection point and having a non-linear shape and a second taper positioned adjacent the second connection point.

Stacked superconducting integrated circuits with three dimensional resonant clock networks are described. An apparatus, including a first superconducting integrated circuit having a first clock distribution network for distributing a first clock signal in the first superconducting integrated circuit, is provided. The apparatus further includes a second superconducting integrated circuit, stacked on top of the first superconducting integrated circuit, having a second clock distribution network for distributing a second clock signal in the second superconducting integrated circuit, where each of the first clock distribution network and the second clock distribution network comprises a clock structure having a plurality of unit cells, where each of the plurality of unit cells includes at least one spine and at least one stub, the at least one stub inductively coupled to a first superconducting circuit, and where each of the first clock signal and the second clock signal has a same resonant frequency.

A method for manipulating a group of quantum dots of a quantum dots matrix, called target group, each target group including a quantum dot and containing a charged particle, the matrix being connected to a reservoir of charged particles, each target group being defined by a potential barrier, each charged particle being a carrier of a charge and spin, the method including, for each target group, a total isolation procedure of the target group relative to the other quantum dots, the potential barrier separating the target group of quantum dots of the matrix adjacent to the target group being configured so that the charged particle(s) contained in the target group cannot cross the potential barrier in order to be moved to the adjacent quantum dots or to the reservoir even when such a transition is authorised from an energy standpoint; and maintaining the target group in the completely isolated regime.

A vector signal generator is capable of operating on microwave frequencies. It comprises a microwave resonator, an output for coupling microwave photons out of said microwave resonator, and a Josephson junction or junction array coupled to the microwave resonator for emitting microwave signals into the microwave resonator. A biasing circuit is provided for applying a bias to the Josephson junction or junction array. A tunable attenuator is coupled to said microwave resonator.

A quantum processing unit is disclosed. The quantum processing unit includes at least one superconducting qubit that is based on phase-biased linear and non-linear inductive-energy elements. A superconducting phase difference across the linear and non-linear inductive-energy elements is biased, for example, by an external magnetic field, such that quadratic potential energy terms of the linear and non-linear inductive-energy elements are cancelled at least partly. In a preferred embodiment, such cancellation is at least 30%. The partial cancellation of the quadratic potential energy terms makes it possible to implement a high-coherence high-anharmonicity superconducting qubit design.

Systems and methods related to low power cryo-CMOS circuits with non-volatile threshold voltage offset compensation are provided. A system includes a plurality of devices configured to operate in a cryogenic environment, where a first distribution of a threshold voltage associated with the plurality of devices has a first value indicative of a measure of spread of the threshold voltage. The system further includes control logic, coupled to each of the plurality of devices, configured to modify a threshold voltage associated with each of the plurality of devices such that the first distribution is changed to a second distribution having a second value of the measure of spread of the threshold voltage representing a lower variation among threshold voltages of the plurality of devices.