Apparatus and methods for removing leakage from a qubit. In one aspect, an apparatus includes one or more qubits, wherein each qubit facilitates occupation of at least one of a plurality of qubit levels, the qubit levels including two computational levels and one or more non-computational levels that are each higher than the computational levels, wherein the qubit facilitates transitions between qubit levels associated with a corresponding transition frequency; a cavity, wherein the cavity defines a cavity frequency; one or more couplers coupling each qubit to the cavity; one or more couplers coupling the cavity to an environment external to the one or more qubits and the cavity; a frequency controller that controls the frequency of each qubit such that, for each qubit, the frequency of the qubit is adjusted relative to the cavity frequency such that a population of a non-computational level is transferred to the cavity.

Systems and techniques that facilitate mapping a heavy-hex qubit connection topology to a rectilinear physical qubit layout are provided. In various embodiments, a device can comprise a qubit lattice on a substrate. In various aspects, the qubit lattice can comprise one or more first qubit tiles. In various cases, the one or more first qubit tiles can have a first shape. In various instances, the qubit lattice can further comprise one or more second qubit tiles. In various cases, the one or more second qubit tiles can have a second shape. In various aspects, the one or more first qubit tiles can be tessellated with the one or more second qubit tiles. In various embodiments, the qubit lattice can exhibit a rectilinear physical layout. In various embodiments, the one or more first qubit tiles tessellated with the one or more second qubit tiles can form a heavy-hex qubit connection topology in the rectilinear physical layout of the qubit lattice. In various embodiments, one of the one or more first qubit tiles can have twelve qubits and twelve interqubit connection buses. In various cases, one of the one or more second qubit tiles can have twelve qubits and twelve interqubit connection buses. In various embodiments, adjacent qubit tiles in the heavy-hex qubit connection topology can share three qubits. In various embodiments, a qubit tile in the heavy-hex qubit connection topology can be adjacent to four qubit tiles having a different shape than the qubit tile. In various cases, the qubit tile can be adjacent to two qubit tiles having a same shape as the qubit tile.

A method and a device for preparing an inductance element, an inductance element, and a superconducting circuit are provided. The method includes acquiring a compound for preparing an inductance element, a superconducting coherence length and a magnetic field penetration depth of the compound meeting a preset condition; and annealing the compound to cause decomposition between a non-superconductor phase and a superconductor phase in the compound to generate the inductance element, the kinetic inductance of the inductance element being greater than the geometric inductance of the inductance element.

Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer and a barrier layer; a first gate metal above the quantum well stack, wherein the barrier layer is between the first gate metal and the quantum well layer; and a second gate metal above the quantum well stack, wherein the barrier layer is between the second gate metal and the quantum well layer, and a material structure of the second gate metal is different from a material structure of the first gate metal.

An electric circuit includes a plurality of superconducting components, each of the plurality of superconducting components having: a respective first terminal; a respective second terminal; and a respective input. The electric circuit further includes a bias current source electrically-connected to the respective first terminal of each of the plurality of superconducting components. The bias current source is configured to provide a bias current adapted to cause the electric circuit to function as a logical OR gate on the respective inputs of the plurality of superconducting components. The electric circuit further includes an output node adapted to output a state of the logical OR gate.

In an embodiment, a fabrication method comprises forming first and second electrodes over a substrate that includes a nanowire that extends between, and beneath portions of, the first and second electrodes. The method also includes forming a mask structure that defines at least one opening over a portion of the nanowire and defines at least one overhang portion over a gap between the substrate and the mask. The method further includes depositing a first gate electrode on the substrate and overlapping a third region of the nanowire, and depositing a second gate electrode on the substrate and overlapping a fourth region of the nanowire. The depositing of the first gate electrode includes depositing conductive material through the at least one opening from a first oblique angle, and the depositing of the second gate electrode includes depositing conductive material through the at least one opening from a second oblique angle.

Techniques for modifying the Josephson potential of a transmon qubit by shunting the transmon with an inductance are described. The inclusion of this inductance may increase the confined potential of the qubit system compared with the conventional transmon, which may lead to a transmon qubit that is stable at much higher drive energies. The inductive shunt may serve the purpose of blocking some or all phase-slips between the electrodes of the qubit. As a result, the inductively shunted transmon may offer an advantage over conventional devices when used for applications involving high energy drives, whilst offering few to no drawbacks in comparison to conventional devices when used at lower drive energies.

A superconducting readout system employing a microwave transmission line, and a microwave superconducting resonator communicatively coupled to the microwave transmission line, and including a superconducting quantum interference device (SQUID), may be advantageously calibrated at least in part by measuring a resonant frequency of the microwave superconducting resonator in response to a flux bias applied to the SQUID, measuring a sensitivity of the resonant frequency in response to the flux bias, and selecting an operating frequency and a sensitivity of the microwave superconducting resonator based at least in part on a variation of the resonant frequency as a function of the flux bias. The flux bias may be applied to the SQUID by an interface inductively coupled to the SQUID. Calibration of the superconducting readout system may also include determining at least one of a propagation delay, a microwave transmission line delay, and a microwave transmission line phase offset.

Novel and useful quantum structures having a continuous well with control gates that control a local depletion region to form quantum dots. Local depleted well tunneling is used to control quantum operations to implement quantum computing circuits. Qubits are realized by modulating gate potential to control tunneling through local depleted region between two or more sections of the well. Complex structures with a higher number of qdots per continuous well and a larger number of wells are fabricated. Both planar and 3D FinFET semiconductor processes are used to build well to gate and well to well tunneling quantum structures. Combining a number of elementary quantum structure, a quantum computing machine is realized. An interface device provides an interface between classic circuitry and quantum circuitry by permitting tunneling of a single quantum particle from the classic side to the quantum side of the device. Detection interface devices detect the presence or absence of a particle destructively or nondestructively.