A single poly non-volatile memory device that includes: a first type lower well; first and second wells separately formed in an upper portion of the first type lower well; a source electrode, a selection transistor, a sensing transistor, and a drain electrode sequentially disposed in an upper portion of the first well. A control gate is formed in an upper portion of the second well with separated on an opposite side of the source electrode from the first well and connected to the gate of the sensing transistor.

A single poly non-volatile memory device that includes: a first type lower well; first and second wells separately formed in an upper portion of the first type lower well; a source electrode, a selection transistor, a sensing transistor, and a drain electrode sequentially disposed in an upper portion of the first well. A control gate is formed in an upper portion of the second well with separated on an opposite side of the source electrode from the first well and connected to the gate of the sensing transistor.

In the memory structure, a pair of gate stack structures is on a first dielectric layer and separated from each other. Each of the gate stack structures includes a word line and a second dielectric layer. A third dielectric layer is on the sidewall of the gate stack structures. A pair of floating gates is between the gate stack structures. Each of the floating gates is on the third dielectric layer on the sidewall of the corresponding gate stack structure. The top surface of the floating gates is not higher than the that of the second dielectric layer. A fourth dielectric layer covers the first and third dielectric layers, and the floating gates. A control gate is on the fourth dielectric layer between the floating gates. A doped region is in the substrate beside the gate stack structures. An erase gate is above the control gate and the floating gates.

A three-dimensional semiconductor device includes a lower substrate, a plurality of lower transistors disposed on the lower substrate, an upper substrate disposed on the lower transistors, a plurality of lower conductive lines disposed between the lower transistors and the upper substrate, and a plurality of upper transistors disposed on the upper substrate. At least one of the lower transistors is connected to a corresponding one of the lower conductive lines. Each of the upper transistors includes an upper gate electrode disposed on the upper substrate, a first upper source/drain pattern disposed in the upper substrate at a first side of the upper gate electrode, and a second upper source/drain pattern disposed in the upper substrate at a second, opposing side of the upper gate electrode. The upper gate electrode includes silicon germanium (SiGe).

A memory structure and a manufacturing method thereof are provided. In the memory structure, a first dielectric layer is disposed on a substrate; a pair of gate stack structures is disposed on the first dielectric layer and each gate stack structure includes a word line, an erase gate and a second dielectric layer; a third dielectric layer is disposed on the surfaces of the gate stack structures; a pair of floating gates is disposed between the gate stack structures and located respectively on sidewalls of the gate stack structures, and top surfaces of the floating gates are lower than those of the erase gates; a fourth dielectric layer covers the first and third dielectric layers and the floating gates; a control gate is disposed on the fourth dielectric layer between the floating gates; and a doped region is disposed in the substrate beside the gate stack structures.

A method for forming a memory device is provided. The method includes forming a floating gate on a substrate, and forming a control gate on the floating gate. The method also includes forming a mask layer on the control gate, and forming a spacer on a sidewall of the mask layer, wherein a sidewall of the control gate and a sidewall of the floating gate is covered by the spacer. The method further includes performing an ion implantation process to implant a dopant into a top portion of the spacer, and performing a wet etching process to expose the sidewall of the control gate.

A nonvolatile memory structure includes a substrate, a select transistor, and a floating-gate transistor. The substrate includes an oxide defined (OD) region and an erase region. The select transistor is disposed on the OD region, and the floating-gate transistor is disposed on the OD region between the select transistor and the erase region, wherein the floating gate has an extended portion capacitively coupled to the erase region, and the extended portion has an extending direction parallel to a first direction. The OD region further has an addition region protruding in a second direction and partially overlapped with the floating gate, in which the second direction is vertical to the first direction.

A vertical semiconductor device may include a stacked structure, a channel structure and a lower connection structure. The stacked structure may include insulation layers and gate electrodes alternately repeatedly stacked. The stacked structure may be spaced apart from an upper surface of a substrate. The channel structure may include a charge storage structure and a channel. The channel structure may pass through the stacked structure. The lower connection structure may be formed on the substrate. The lower connection structure may be electrically connected with the channel and the substrate. A sidewall of the lower connection structure may include a protrusion disposed at a central portion of the sidewall from the upper surface of the substrate in a vertical direction. The vertical semiconductor device may have a high reliability.

A bonded assembly includes a first memory die containing a first three-dimensional memory device, a second memory die containing a second three-dimensional memory device, and a support die bonded to the first memory die and comprising a peripheral circuitry configured to control the first three-dimensional memory device and the second three-dimensional memory device. The first memory die includes multiple rows of first-die proximal bonding pads, multiple rows of first-die distal bonding pads, and a plurality of first-die laterally-shifting electrically conductive paths connecting a respective one of the first-die proximal bonding pads and a respective one of the first-die distal bonding pads that is laterally offset from the respective one of the first-die proximal bonding pads. The first memory die and the second memory die can have an identical layout, and electrical connections can be shifted through the first memory die by the offset distance.

A non-volatile memory cell and array structure is disclosed situated within a high voltage region of an integrated circuit. The cell utilizes capacitive coupling based on an overlap between a gate and a drift region to impart a programming voltage. Programming is effectuated using a drain extension which can act to inject hot electrons. The cell can be operated as a one-time programmable (OTP) or multiple-time programmable (MTP) device. The fabrication of the cell relies on processing steps associated with high voltage devices, thus avoiding the need for additional masks, manufacturing steps, etc.