A semiconductor device includes a plurality of drift regions of a plurality of field effect transistor structures arranged in a semiconductor substrate. The plurality of drift regions has a first conductivity type. The semiconductor device further includes a plurality of compensation regions arranged in the semiconductor substrate. The plurality of compensation regions has a second conductivity type. Each drift region of the plurality of drift regions is arranged adjacent to at least one compensation region of the plurality of compensation regions. The semiconductor device further includes a Schottky diode structure or metal-insulation-semiconductor gated diode structure arranged at the semiconductor substrate.

A semiconductor device includes: a plurality of trenches provided in an upper surface of a semiconductor substrate; trench electrodes each provided in a corresponding one of the trenches; a first semiconductor layer of a first conductivity type provided in a first range interposed between adjacent ones of the trenches; a second semiconductor layer of a second conductivity type; a third semiconductor layer of the first conductivity type; an interlayer insulation film provided on the upper surface of the semiconductor substrate and including a plurality of contact holes; a first conductor layer provided in each of the contact holes; and a surface electrode provided on the interlayer insulation film and connected to each of the first conductor layers.

A VTMOS transistor in semiconductor material of a first type of conductivity includes a body region of a second type of conductivity and a source region of the first type of conductivity. A gate region extends into the main surface through the body region and is insulated from the semiconductor material. A region of the gate region extends onto the main surface is insulated from the rest of the gate region. An anode region of the first type of conductivity is formed into said insulated region, and a cathode region of the second type of conductivity is formed into said insulated region in contact with the anode region; the anode region and the cathode region define a thermal diode electrically insulated from the chip.

A semiconductor device of embodiments includes: an element region including a transistor, a first diode, and a first contact portion; a termination region surrounding the element region and including a second contact portion; and an intermediate region provided between the element region and the termination region and not including the transistor, the first diode, the first contact portion, and the second contact portion. The element region includes a first electrode, a second electrode, a gate electrode, a silicon carbide layer, and a gate insulating layer. The termination region includes a first wiring layer electrically connected to the first electrode, the second electrode, and the silicon carbide layer. The intermediate region includes the silicon carbide layer. The width of the intermediate region in a direction from the element region to the termination region is equal to or more than twice the thickness of the silicon carbide layer.

Provided is a semiconductor power device. The device includes: at least one p-type body region located on the top of an n-type drift region, a first n-type source region and a second n-type source region located within the p-type body region, a first gate structure configured to control a first current channel between the first n-type source region and the n-type drift region to be turned on or off; and a second gate structure configured to control a second current channel between the second n-type source region and the n-type drift region to be turned on or off. The second gate structure is recessed in the n-type drift region.

A semiconductor device includes MOSFET cells having a drift region of a first conductivity type. A first and second active area trench are in the drift region. A split gate uses the active trenches as field plates or includes planar gates between the active trenches including a MOS gate electrode (MOS gate) and a diode gate electrode (diode gate). A body region of the second conductivity type in the drift region abutts the active trenches. A source of the first conductivity type in the body region includes a first source portion proximate to the MOS gate and a second source portion proximate to the diode gate. A vertical drift region uses the drift region below the body region to provide a drain. A connector shorts the diode gate to the second source portion to provide an integrated channel diode. The MOS gate is electrically isolated from the first source portion.

According to one embodiment, a semiconductor device is provided. The semiconductor device has a first region formed of semiconductor and a second region formed of semiconductor which borders the first region. An electrode is formed to be in ohmic-connection with the first region. A third region is formed to sandwich the first region. A first potential difference is produced between the first and the second regions in a thermal equilibrium state, according to a second potential difference between the third region and the first region.

A power MOSFET includes an insulating layer, a first conductivity type doping layer situated on a bottom of the insulating layer, a second conductivity type body situated on a bottom of the first conductivity type doping layer, a gate electrode adjacent to the bottom of the insulating layer and covered with an insulating film in other regions and projected to penetrate the second conductivity type body, and a source electrode including a first region situated on a top of the insulating layer and a second region in contact with the first conductivity type doping layer by penetrating the insulating layer.

A synchronous rectifier is described that includes a transistor device that has a gate terminal, a source terminal, a drain terminal, and a field-plate electrode. The field-plate electrode of the transistor device includes an integrated diode. The integrated diode is configured to discharge a parasitic capacitance of the transistor device during each switching operation of the synchronous rectifier. In some examples, the integrated diode is also configured to charge the parasitic capacitance of the transistor device during each switching operation of the synchronous rectifier.

A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.