Semiconductor device and method for fabricating the same

Abstract

A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.

Claims

1. A method of manufacturing a semiconductor device including a MISFET forming region of a semiconductor substrate and a peripheral region of the semiconductor substrate, comprising steps of: (a) forming a first semiconductor layer of a first conductive type in the semiconductor substrate; (b) forming a field insulating film in the peripheral region; (c) forming a well region of the second conductive type opposite to the first conductive type in the peripheral region such that the well region is also formed under the field insulating film; (d) forming a first trench in the MISFET forming region, and forming a second trench in the peripheral region such that the second trench penetrates the well region and a bottom of the second trench is located at the first semiconductor layer, wherein the first and second trenches are unified; (e) forming a first gate insulating film in the first trench, and forming a second gate insulating film in the second trench; (f) forming a gate electrode in the first trench through the first gate insulating film, and forming a gate wiring formed in the second trench through the second gate insulating film such that the gate wiring is also formed over the field insulating film, wherein the gate electrode and the gate wiring are unified; (g) after the step (f), forming a second semiconductor layer of the second conductive type in the first semiconductor layer of the MISFET forming region; (h) after the step (f), forming a third semiconductor layer of the first conductive type in the second semiconductor layer; (i) after the steps (g) and (h), forming a contact hole formed in the second and third semiconductor layers such that a bottom of the contact hole is located at the second semiconductor layer; and (j) forming a source wiring in the contact hole and connected to the second and third semiconductor layers.

2. The method of manufacturing a semiconductor device according to claim 1, wherein an impurity concentration of the well region is lower than an impurity concentration of the second semiconductor layer.

3. The method of manufacturing a semiconductor device according to claim 1, wherein a depth of the well region is different form a depth of the second semiconductor layer.

4. The method of manufacturing a semiconductor device according to claim 3, wherein the depth of the well region is lower than the depth of the second semiconductor layer.

5. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a fourth semiconductor layer of the second conductive type in the second semiconductor layer which is arranged at a bottom of the contact hole between the steps (i) and (j), wherein an impurity concentration of the fourth semiconductor layer is higher than an impurity concentration of the second semiconductor layer.

6. The method of manufacturing a semiconductor device according to claim 1, wherein the source wiring is connected to an upper surface of the third semiconductor layer outside the second trench and a side surface of the third semiconductor layer inside the second trench.

7. The method of manufacturing a semiconductor device according to claim 1, wherein the first semiconductor region serves a drain region of a MISFET, wherein the second semiconductor region serves a channel region of the MISFET, and wherein the third semiconductor region serves a source region of the MISFET.

8. The method of manufacturing a semiconductor device according to claim 1, wherein the first conductive type is an n-type, and wherein the second conductive type is a p-type.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a plan view illustrating a semiconductor device according to Embodiment 1 of the present invention;

(2) FIG. 2 is a fragmentary plan view illustrating the semiconductor device according to Embodiment 1 of the present invention;

(3) FIG. 3 is a partial longitudinal cross-sectional view taken along a line a-a of FIG. 2;

(4) FIG. 4 is a longitudinal fragmentary cross-sectional view illustrating, in the order of steps, the semiconductor device according to Embodiment 1 of the present invention;

(5) FIG. 5 is a longitudinal fragmentary cross-sectional view illustrating, in the order of steps, the semiconductor device according to Embodiment 1 of the present invention;

(6) FIG. 6 is a longitudinal fragmentary cross-sectional view illustrating, in the order of steps, the semiconductor device according to Embodiment 1 of the present invention;

(7) FIG. 7 is a longitudinal fragmentary cross-sectional view illustrating, in the order of steps, the semiconductor device according to Embodiment 1 of the present invention;

(8) FIG. 8 is a longitudinal fragmentary cross-sectional view illustrating, in the order of steps, the semiconductor device according to Embodiment 1 of the present invention;

(9) FIG. 9 is a longitudinal fragmentary cross-sectional view illustrating, in the order of steps, the semiconductor device according to Embodiment 1 of the present invention;

(10) FIG. 10 is a longitudinal fragmentary cross-sectional view illustrating, in the order of steps, the semiconductor device according to Embodiment 1 of the present invention;

(11) FIG. 11 is a longitudinal fragmentary cross-sectional view illustrating, in the order of steps, the semiconductor device according to Embodiment 1 of the present invention;

(12) FIG. 12 is a longitudinal fragmentary cross-sectional view illustrating, in the order of steps, the semiconductor device according to Embodiment 1 of the present invention;

(13) FIG. 13 is a longitudinal fragmentary cross-sectional view illustrating, in the order of steps, the semiconductor device according to Embodiment 1 of the present invention;

(14) FIG. 14 is a partially-enlarged fragmentary cross-sectional view illustrating, in the order of steps, the semiconductor device according to Embodiment 1 of the present invention;

(15) FIG. 15 is a partially-enlarged fragmentary cross-sectional view illustrating, in the order of steps, the semiconductor device according to Embodiment 1 of the present invention;

(16) FIG. 16 is a partially-enlarged fragmentary cross-sectional view illustrating, in the order of steps, the semiconductor device according to Embodiment 1 of the present invention;

(17) FIG. 17 is a partially enlarged fragmentary cross-sectional view illustrating, in the order of steps, the semiconductor device according to Embodiment 1 of the present invention;

(18) FIG. 18 is a partially-enlarged fragmentary cross-sectional view illustrating, in the order of steps, the semiconductor device according to Embodiment 1 of the present invention;

(19) FIG. 19 is a partially-enlarged fragmentary cross-sectional view illustrating, in the order of steps, the semiconductor device according to Embodiment 1 of the present invention;

(20) FIG. 20 is a partially-enlarged fragmentary cross-sectional view illustrating, in the order of steps, the semiconductor device according to Embodiment 1 of the present invention;

(21) FIG. 21 is a partially-enlarged fragmentary cross-sectional view illustrating, in the order of steps, the semiconductor device according to Embodiment 1 of the present invention;

(22) FIG. 22 is a partially-enlarged fragmentary cross-sectional view illustrating, in the order of steps, the semiconductor device according to Embodiment 1 of the present invention;

(23) FIG. 23 is a partially-enlarged fragmentary cross-sectional view illustrating, in the order of steps, the semiconductor device according to Embodiment 1 of the present invention;

(24) FIG. 24 is a partially-enlarged fragmentary cross-sectional view illustrating, in the order of steps, the semiconductor device according to Embodiment 1 of the present invention;

(25) FIG. 25 is a partially-enlarged fragmentary cross-sectional view illustrating, in the order of steps, the semiconductor device according to Embodiment 1 of the present invention;

(26) FIG. 26 is a partially-enlarged fragmentary cross-sectional view illustrating, in the order of steps, the semiconductor device according to Embodiment 1 of the present invention;

(27) FIG. 27 is an equivalent circuit view of MISFET having a protective diode disposed thereon according to Embodiment 1 of the present invention;

(28) FIG. 28 is a partially-enlarged fragmentary cross-sectional view illustrating, in the order of steps, the semiconductor device according to another embodiment of the present invention; and

(29) FIG. 29 is a partially-enlarged fragmentary cross-sectional view illustrating, in the order of steps, the semiconductor device according to the another embodiment 1 of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(30) The embodiments of the present invention will hereinafter be described. In all the drawings for describing the embodiments, like members of a function will be identified by like reference numerals and overlapping descriptions will be omitted.

Embodiment 1

(31) FIG. 1 is a plan view illustrating a power MISFET having a trench-gate structure, which will be the semiconductor device according to Embodiment 1 of the present invention, FIG. 2 is a fragmentary plan view illustrating the portion a of FIG. 1 in an enlarged scale and FIG. 3 is a longitudinal cross-sectional view taken along a line a-a of FIG. 2.

(32) The MISFET of this embodiment is formed on a semiconductor substrate obtained, for example, by forming an epitaxial layer 2 on an n.sup.+-type semiconductor body 1, for example, made of single crystal silicon by the epitaxial growth technique. This MISFET is disposed in the form of a rectangular ring along the outer periphery of the semiconductor substrate and it is formed within a region surrounded by a field insulating film 3 (shown by a double slash in FIG. 2) having a rectangular portion inside of the corner. Within the above-described region, a plurality of hexagonal or flat pentagonal cells (semiconductor island region) having a trench-gate structure are disposed regularly and a mesh-gate structure wherein gates are two-dimensionally disposed in the lattice form and cells are connected in parallel each other is formed. The trench-gate structure is thus formed to separate the main surface of the semiconductor substrate into semiconductor island regions for cells.

(33) In each cell, that is, in each semiconductor island region, an n.sup.-type first semiconductor layer 2a formed over the semiconductor body 1 serves as a drain region, a p-type second semiconductor layer 2b formed over the first semiconductor layer 2a serves as a base region wherein a channel is to be formed, and an n.sup.+-type third semiconductor layer 2c formed over the second semiconductor layer 2b serves as a source region, thus forming a vertical FET.

(34) A trench gate (gate electrode) 4 is formed, via a gate insulating film 5, in a trench which extends from the main surface of the semiconductor substrate to the n.sup.-type second semiconductor layer 2a which will be a drain region. As the trench gate 4, for example impurity-introduced polycrystalline silicon is employed, while the gate insulating film 5 is made of a multilayer film obtained, for example, by successively stacking a thermal oxide film of about 27 nm thick and a deposition film of about 50 nm thick.

(35) As illustrated in FIGS. 19 to 21 which will be described later, the upper surface 4a of the trench gate 4 of this embodiment is formed higher than the surface of the third semiconductor layer 2c, which will be a source region, that is, the main surface of the semiconductor substrate. Such a constitution makes it possible to prevent the trench gate 4 from getting out of the source region, that is, prevent occurrence of a source offset even if the source region is made shallow. The trench gate 4 is desired to have a substantially flat or convex upper surface.

(36) The trench gates 4 of adjacent cells are connected each other, thus forming a mesh-gate structure wherein they are disposed two-dimensionally in the form of a lattice. The trench gate 4 of each of the cells positioned at the outer periphery is connected, for example, with a polycrystalline-silicon-made gate wiring 6 in the vicinity at the outer periphery of a semiconductor chip.

(37) The gate wiring 6 is electrically connected with a gate guard ring 8 (partially shown by a broken line in FIG. 2) which is formed thereover through an interlayer insulating film 7 and is, for example, made of silicon-containing aluminum. The gate guard ring 8 is integrated with a rectangular gate electrode 9 (partially shown by a broken line in FIG. 2) which is disposed at the rectangular portion of the field insulating film 3. The gate electrode 9 has a connecting region (shown by a broken line in FIG. 1) with the gate 4.

(38) A third semiconductor layer 2c, which will be a source, is electrically connected with a source wiring 10 (partially shown by a broken line in FIG. 2) which is formed over the main surface of the semiconductor substrate through the interlayer insulating film 7 and is, for example, made of silicon-containing aluminum. The source wiring 10 has a connecting region (shown by a broken line in FIG. 1) with the third semiconductor layer 2c, which will be a source. This source wiring 10 is electrically connected with not only third semiconductor layer 2c which will be a source but also a p.sup.+-type contact layer 11 disposed in the second semiconductor layer 2b to make the base potential, that is, the potential of a channel forming region constant.

(39) As is illustrated in FIG. 3 or 22, a protective diode 12 having a back-to-back structure is disposed between the gate and source. In the protective diode 12, the n.sup.+-type semiconductor regions 12a and p-type semiconductor regions 12b are alternately formed in the form of a concentric ring, and with the n.sup.+-type semiconductor regions 12 at both ends are electrically connected the gate electrode 9 and source wiring 10, respectively. A shown in the circuit diagram of FIG. 27, the protective diode is disposed between the gate and the source for protecting breakdown of the gate insulating film from the surge from the source.

(40) At the outer periphery of the field insulating film 3, disposed is a source guard ring 13 obtained by connecting an n.sup.+-type semiconductor region 13a disposed over the main surface of the semiconductor substrate with a wiring 13b (partially shown by a broken line in FIG. 2), for example, made of silicon-containing aluminum. Similar to the source wiring 10, the wiring 13b of the source guard ring 13 is connected with the n.sup.+-type semiconductor region 12a of the protective diode 12.

(41) The gate wiring 6 and gate guard ring 8 are disposed over the field insulating film 3 disposed in the form of a rectangular ring, while the gate electrode 9 and protective diode 12 are disposed over the rectangular portion disposed at the corner of the field insulating film 3.

(42) Along the field insulating film 3 in the rectangular ring form, a p-type well 14 is formed therebelow. By connecting the p-type well 14 with the terminal portion of the trench gate 4 through the gate insulating film 5, a depletion layer can be gently extended below the field insulating film 3 and discontinuity of the depletion layer can be prevented. The p-type well 14 therefore functions as a field relaxing portion for relaxing the electric field at the terminal portion of the trench gate 4.

(43) All over the main surface of the semiconductor substrate, a protective insulating film 15 is formed, for example, by stacking polyimide on a silicon oxide film, which has been obtained by plasma CVD using as a main source gas tetraethoxysilane (TEOS), to cover the gate guard ring 8, gate electrode 9, source wiring 10 and source guard ring 13. A contact hole is made in this protective insulating film 15 to partially expose the gate electrode 9 and source wiring 10. The gate electrode 9 and source wiring 10 to be exposed by this contact hole will become connecting regions with the gate and source, respectively. Electric connection to each of these connecting regions is conducted by wire bonding or the like.

(44) As the connecting region with the drain, a drain electrode 16 which is electrically conductive with the n.sup.+-type semiconductor substrate 1 is formed, for example, as a nickel-titanium-nickel-silver laminated film all over the reverse side of the semiconductor substrate, and the drain electrode 16 is electrically connected with a lead frame by a conductive adhesive.

(45) A fabrication method of the above-described semiconductor device will next be described based on FIGS. 4 to 26.

(46) Over the n.sup.+ semiconductor body 1, for example, made of single crystal silicon having arsenic (As) introduced therein, an n.sup. type epitaxial layer 2 having a lower concentration than the semiconductor body 1 is formed to give a thickness of about 5 m by epitaxial growth. A silicon oxide film of about 40 nm thick is then formed over the main surface of this semiconductor substrate, for example, by thermal oxidation, followed by the formation, as a mask of a silicon nitride (SiN) film over this silicon oxide film in the rectangular ring form along the outer periphery of the semiconductor substrate. A field insulating film 3 having a rectangular portion inside of the corner is then formed by thermal oxidation in self alignment with the silicon nitride film. Along the inner periphery of the field insulating film 3, ions, for example, boron (B) are implanted and the impurities thus introduced are diffused, whereby a p-type well 14 which will be a field relaxing portion is formed as shown in FIG. 4. The impurity concentration of the p-type well 14 is, for example, set equal to or lower than that of the second semiconductor layer 2b.

(47) A silicon oxide film is then formed over the main surface of the semiconductor substrate. Within a cell forming region surrounded by the field insulating film 3, the silicon oxide film is patterned to form a contact hole which exposes a portion of the main surface of the semiconductor substrate over which a trench gate (gate electrode) of a mesh-gate structure wherein gates are two-dimensionally arranged in the lattice form is formed. With this silicon oxide film as a mask, a trench of, for example, about 1.6 m thick is formed in the main surface of the semiconductor substrate by dry etching. This trench separates the main surface of the semiconductor substrate into plural semiconductor island regions 2 on which a cell is to be formed.

(48) The trench formation is completed, for example, by making a trench by dry etching, removing the silicon oxide film, which will be a mask, by wet etching and then chemical dry etching to remove the angular portion at the bottom edge. A gate insulating film 5 is then formed by stacking a silicon oxide film of about 50 nm thick over a thermal oxide film of about 27 nm thick by CVD (Chemical Vapor Deposition) as illustrated in FIGS. 5 and 15.

(49) All over the main surface of the semiconductor substrate including the inside of the trench, a polycrystalline silicon film 4 which will be a conductive film of the trench gate, is formed by CVD. Into this polycrystalline silicon film 4, impurities (ex. phosphorus) for reducing its resistance are introduced during or after deposition. The impurity concentration is set to fall within a range of from 1E18/cm.sup.3 to 1E21/cm.sup.3 (110.sup.18 to 110.sup.21/cm.sup.3), which is higher than the that of the n.sup.-type epitaxial layer 2 (main surface of the semiconductor substrate). Owing to such a high impurity concentration, accelerated oxidizing phenomenon which will be described later can be used effectively. This stage is illustrated in FIG. 6.

(50) After the polycrystalline silicon film 4 is etched back by multistage oxidation wherein oxidation and etching are repeated several times and is thereby flattened, it is removed by etching, whereby a trench gate 4 is formed in the trench. Simultaneously with this etching, a gate wiring 6 connected with the trench gate 4 and a polycrystalline silicon film 9a which will lie below the gate electrode 9 are formed over the rectangular ring portion of the field insulating film 3, which are illustrated in FIGS. 7 and 16.

(51) The flattening upon formation of the trench gate 4 prevents the formation of a concave portion on the upper surface of the trench gate 4. If the concave portion is formed, formation of an insulating film in the subsequent step is not sufficient on this concave portion and at the same time, the progress of etching is accelerated, which happens to expose the trench gate 4. The above-described flattening prevents such exposure of the trench gate 4. Flattening can alternatively be conducted by CMP (Chemical Mechanical Polishing).

(52) The unnecessary portion of the silicon oxide film remaining on the main surface of the semiconductor substrate is then removed. After exposure of the main surface of the semiconductor substrate, an insulating film 17 made of, for example, a silicon oxide film, is formed by thermal oxidation all over the main surface of the semiconductor substrate and trench gate 4. Since the impurity concentration of the polycrystalline silicon film which constitutes the trench gate 4 is higher than that of the main surface of the semiconductor substrate, the insulating film 17 is formed, by the accelerated oxidation phenomenon, to be thicker on the trench gate 4 (thickness: L1) than on the main surface of the semiconductor substrate (thickness: L2). Upon formation of the insulating film 17 having a greater film thickness (L1) over the trench gate 4 by accelerated oxidation, the insulating film 17 is formed over the main surface of the low-concentration epitaxial layer 2 so that the film thickness (L1) of the insulating film over the trench gate 4 can be made greater than that (L2) over the main surface of the epitaxial layer 2. This stage is illustrated in FIGS. 8 and 17.

(53) The insulating film 17 is then removed by dry etching and the main surface of the semiconductor substrate is exposed with the thickly-formed insulating film 17 being left on the trench gate 4, as illustrated in FIGS. 9 and 18.

(54) Dry etching is then conducted using a CF.sub.4 gas to selectively remove silicon, relative to silicon oxide, from the main surface of the semiconductor substrate, whereby the main surface 2a of the semiconductor substrate is made lower than the upper surface 4a of the trench gate 4. In other words, the upper surface 4a of the trench gate 4 covered with silicon oxide is formed equal to or higher than the surface of the third semiconductor layer 2c, which will be a source region, that is, the main surface of the semiconductor substrate, as illustrated in FIGS. 10 and 19. By oxidation, the etching damage is removed and an oxide film 17a for reinforcing the gate insulating film 5 and insulating film 17 are formed as illustrated in FIG. 20.

(55) After formation of an insulating film 12c made of silicon oxide, a polycrystalline silicon film is deposited over the insulating film 12c. Then, p-type impurities are introduced into the polycrystalline silicon film, followed by patterning, on the rectangular portion of the field insulating film 3, into a concentric ring form surrounding the polycrystalline silicon film 9a on the gate electrode 9. Upon patterning, the insulating film 12c serves as an etching stopper for preventing the trench gate 4 and gate wiring 6 from being patterned. Then, an n.sup.+-type semiconductor region 12a is formed, for example, by ion implantation, whereby a protective diode 12 having the n.sup.+-type semiconductor region 12a and p-type semiconductor region 12b formed alternately in the concentric ring form is formed as illustrated in FIGS. 11 and 22.

(56) Ions such as p-type impurities (ex. boron) are then implanted all over the surface of the epitaxial layer 2, followed by diffusion treatment for about 100 minutes in a 1% O.sub.2-containing nitrogen gas atmosphere at about 1100 C., whereby a p-type second semiconductor layer 2b, which will be a channel forming region, is formed. Then, ions such as n-type impurities (ex. arsenic) are selectively implanted, followed by annealing treatment for about 30 minutes in a 1% O.sub.2-containing nitrogen gas atmosphere at about 950 C., whereby a third semiconductor layer 2c, which will be a source region, is formed. The deeper portion of the epitaxial layer 2 into which impurities have not been introduced, more specifically, a portion of the epitaxial layer 2 lying between the second semiconductor layer 2b and semiconductor body 1 becomes the first semiconductor layer 2a serving as a drain region. The number of the steps may be reduced by simultaneously conducting ion implantation of the n.sup.+-type semiconductor region 12a and the first semiconductor layer 2a. This stage is illustrated in FIGS. 12 and 21.

(57) Since the second semiconductor layer 2b, which will be a channel forming region, and the third semiconductor layer 2c, which will be a source region, are formed by ion implantation after the main surface 2d of the semiconductor substrate is lowered relative to the upper surface 4a of the trench gate 4 by causing the semiconductor substrate to retreat, the profile in the depth direction in the semiconductor substrate 2 and the depth of each of the second semiconductor layer 2b and third semiconductor layer 2c can be controlled precisely, which makes it possible to accelerate thinning of the second semiconductor layer 2b and third semiconductor layer 2c. In short, the depth of the second semiconductor layer 2b can be controlled precisely, making it possible to control the channel length precisely.

(58) All over the main surface of the semiconductor substrate, an interlayer insulating film 7 is formed by depositing, for example, BPSG to give a film thickness of about 500 nm.

(59) By anisotropic dry etching using a CHF.sub.3 gas, a contact hole CH (contact hole) is made in the interlayer insulating film 7 to expose each of the third semiconductor layer 2c which will be a source region, gate wiring 6, source guard ring semiconductor region 13a and a connecting region with the protective diode. All over the main surface of the semiconductor substrate including the inside of each of the contact holes, a conductive film (metal film) made of, for example, silicon-containing aluminum is formed. By patterning of the metal film, the gate guard ring 8, gate electrode 9, source wiring 10 and source guard ring 13 are formed, as illustrated in FIG. 12.

(60) Conventionally, a contact layer 11 has been formed to extend from the main surface of the semiconductor substrate to the second semiconductor layer 2b, and with this contact layer 11 and the third semiconductor layer 2c around the contact layer 11, the source wiring 10 has been connected. In this embodiment, on the other hand, a contact hole CH is formed to extend to the second semiconductor layer 2b by etching as illustrated in FIG. 23, followed by direct introduction of p-type impurities such as boron into the second semiconductor layer 2b exposed by the contact hole CH as illustrated in FIG. 24. The p-type contact layer 11 is formed deeply by such a constitution, leading to a reduction in the generation amount of avalanche. Upon formation of the source, a mask for covering the contact layer 11 becomes unnecessary so that a subsequent photoresist step can be omitted. If the contact layer 11 is not required at the contact portion of another contact hole CH owing to the fabrication of the device into IC, it is possible to form a contact layer 11 only for a contact hole CH to be electrically connected easily with the source wiring 10 by using another mask covering the contact.

(61) In this Embodiment, as illustrated in FIG. 25, after introduction of impurities from the contact hole CH, silicon oxide is removed from the interlayer insulating film 7 by selective etching relative to silicon in the main surface of the semiconductor substrate, whereby the surface of the third semiconductor layer 2c is exposed in self alignment with the contact hole CH. As illustrated in FIG. 26, such a constitution makes it possible to enlarge the contact area between the third semiconductor layer 2c and source wiring 10, thereby reducing the connection resistance.

(62) In the next place, a protective insulating film 15 which covers therewith the whole main surface of the semiconductor substrate is formed by applying and stacking polyimide onto a silicon oxide film formed by plasma CVD using tetraethoxysilane (TEOS) gas as a main source gas. In the resulting protective insulating film 15, a contact hole to expose the connecting region of each of the gate electrode 9 and the source wiring 10 is formed, followed by polishing treatment on the reverse side of the n.sup.+-type semiconductor body 1. A drain electrode 14 is then formed, for example, by successively depositing and stacking nickel, titanium, nickel and silver on the reverse side as illustrated in FIG. 3.

(63) In this Embodiment, the p-type well 14 is disposed as a field relaxing portion in the form of a rectangular ring. Alternatively, it is possible to make a contact hole in the field insulating film 3 and introducing impurities from this contact hole to have the p-type wells 14 studded below the field insulating film in the ring form. In this constitution, the field relaxing portion can be formed after the formation of the gate wiring 6.

Embodiment 2

(64) In FIGS. 28 and 29, another embodiment of the present invention is illustrated.

(65) This embodiment differs from the above-described one in the step for lowering the main surface 2d of the semiconductor substrate relative to the upper surface 4a of the trench gate 4. This embodiment is substantially similar to the above-described one in the other steps so a description of the other steps is omitted.

(66) The fabricating method of the semiconductor device according to this embodiment will next be described based on FIGS. 28 and 29.

(67) After the step of the above-described embodiment as illustrated in FIG. 18, a photoresist film 30 is for example formed, as illustrated in FIG. 28, over the insulating film 17 overlying the trench gate 4.

(68) With the photoresist film 30 as a mask, the semiconductor substrate 2 is subjected to isotropic etching to selectively etch the semiconductor substrate 2 relative to the insulating films 5, 17, whereby the main surface 2d of the semiconductor substrate is made lower than the upper surface 4a of the trench gate 4 as illustrated in FIG. 29.

(69) The weak insulating film 17 formed by accelerated oxidation is thus protected by causing the surface of the semiconductor substrate to retreat with the photoresist film 30 over the insulating film 17 as a mask, which makes it possible to prevent the invasion of an Si etching gas into the trench gate 4 and, in turn, etching of the trench gate 4.

(70) After the removal of the photoresist film 30, steps on and after the formation of an insulating film 17a, that is, the steps on and after FIG. 20, are conducted in a similar manner to the above-described embodiment, whereby a semiconductor device is formed.

(71) According to this embodiment, it becomes possible to protect the weak insulating film 17 and prevent the trench gate 4 from being etched during etching of the semiconductor substrate 2 for causing the surface of the semiconductor substrate to retreat, leading to an improvement in the reliability of a semiconductor device.

(72) The inventions made by present inventors have so far been described specifically based on the above-described embodiments. It should however be borne in mind that the present invention is not limited by them, but can be modified within an extent not departing from the scope of the present invention.

(73) The present invention can be adapted, for example, to IGBT (Integrated Gate Bipolar Transistor), as well as power MISFET.

(74) Advantages of the representative inventions, among the inventions disclosed by the present application, will next be described briefly.

(75) (1) The present invention is effective for preventing a source offset by forming the upper surface of the trench-gate conductive layer equal to or higher than the main surface of the semiconductor substrate.

(76) (2) In the present invention, the above-described advantage (1) makes it possible to promote thinning of a source.

(77) (3) In the present invention, the above-described advantage (2) makes it possible to promote miniaturization of a cell.