The semiconductor device includes a semiconductor layer which has a main surface, a switching device which is formed in the semiconductor layer, a first electrode which is arranged on the main surface and electrically connected to the switching device, a second electrode which is arranged on the main surface at an interval from the first electrode and electrically connected to the switching device, a first terminal electrode which has a portion that overlaps the first electrode in plan view and a portion that overlaps the second electrode and is electrically connected to the first electrode, and a second terminal electrode which has a portion that overlaps the second electrode in plan view and is electrically connected to the second electrode.

An embodiment of a SiC transistor includes a SiC substrate and a layer of metallization, which forms a drain terminal of the transistor. The SiC substrate includes a first horizontal N-doped region disposed above the layer of metallization, a second horizontal region disposed above the first horizontal region and including an N-doped region beside a P-doped region, a gate conductor disposed above the N-doped region, an N-doped source disposed above the P-doped region, and a source metal that bisects the source and that is electrically coupled to the P-doped region and the source. As compared to a SiC power transistor lacking the second generally horizontal region or the bisected source, an embodiment of the SiC power transistor can have, for a given maximum-blocking-voltage rating, a thinner substrate region, and, therefore, a lower RdsON over a range of transistor-operating temperatures (e.g., at room temperature and at higher temperatures).

Trench-gate MOSFETs use a N+ SiC substrate with a N SiC drift layer. A Si wafer is bonded to the top of the SiC wafer, forming a Si/SiC heterojunction at the interface. Gate trenches are formed in the Si layer, oxidized, and filled with a conductor. Since the gate oxide is only in contact with the Si, and not the SiC, there is no problem with carbon at the gate oxide interface. Also, since the MOSFET is formed in the Si layer, electron mobility near the gates is high. JFET channel regions in the SiC layer pinch off during short circuit, high current conditions to limit drain current and thus achieve a higher short circuit withstand time capability. At the Si/SiC interface, a thin, highly doped n-type layer is formed in the SiC layer that allows tunneling current flowing through the barrier to lower the voltage drop across the heterojunction.

An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal and having a first main surface as an element forming surface, a second main surface at a side opposite to the first main surface, and a plurality of side surfaces connecting the first main surface and the second main surface, and a plurality of modified lines formed one layer each at the respective side surfaces of the SiC semiconductor layer and each extending in a band shape along a tangential direction to the first main surface of the SiC semiconductor layer and modified to be of a property differing from the SiC monocrystal.

A power module apparatus includes a power module having a package configured to seal a perimeter of a semiconductor device, and a heat radiator bonded to one surface of the package; a cooling device having a coolant passage through which coolant water flows, in which the heat radiator is attached to an opening provided on a way of the coolant passage, wherein the heat radiator of the power module is attached to the opening of the cooling device so that a height (ha) and a height (hb) are substantially identical to each other. The power module in which the heat radiator is attached to the opening formed at the upper surface portion of the cooling device can also be efficiently cooled, and thereby it becomes possible to reduce degradation due to overheating.

A silicon carbide semiconductor device has a first semiconductor region of a first conductivity type, provided in a semiconductor substrate, spanning an active region and a termination region. A second semiconductor region of a second conductivity type is provided between a first main surface and the first semiconductor region, in the active region. A device structure having a first pn junction is provided between the first and second semiconductor regions. An outer peripheral portion of the active region is provided between the first main surface and the first semiconductor region in the active region, and constitutes a second-conductivity-type outer peripheral region that surrounds a periphery of the device structure and forms a second pn junction with the first semiconductor region. A first protective film is provided on the first main surface. The first protective film blocks light generated by a forward current passing through the first and second pn junctions.

A semiconductor device and a power conversion device each comprise a drift layer, a gate electrode to face a well region and a source region via a gate insulating film, a source electrode provided on an interlayer insulating film covering the gate electrode and connected to the well region and the source region, a first separation region provided in an active region in which a plurality of MOSFETs each including the well region, the source region, and the gate electrode are arranged in the drift layer, the first separation region being provided to be connected to the drift layer and forming Schottky connection with the source electrode, and a surge current conduction region provided in the active region, and blocks connection between the source electrode and the drift layer, thereby enabling the achievement of a semiconductor device and a power conversion device that exhibit high surge tolerance.

A trench-gate planar-gate semiconductor device with monolithically integrated Schottky barrier diode and Junction Schottky barrier diode, where the semiconductor device includes at least one semiconductor cell. The semiconductor cell includes: a substrate arranged at a bottom surface of the semiconductor cell; a vertical channel section placed above the substrate; a planar channel section formed above the substrate and below a trench that is formed on both sides of the vertical channel section; a Schottky section placed above the substrate; and a Junction Schottky section placed above the substrate. The vertical channel section and the Schottky section are placed in a mesa section of the semiconductor device along a first direction parallel to the bottom surface. The planar channel section and the Junction Schottky section are placed below the trench along the first direction parallel to the bottom surface.

Provided is a semiconductor device comprising a semiconductor substrate which has an upper surface and a lower surface, and which is provided with a diode portion, wherein the diode portion includes a first cathode region of a first conductivity type, and a second cathode region of a second conductivity type, and the first cathode region and the second cathode region are provided alternately in a first direction, and a repetition pitch of the first cathode region and the second cathode region in the first direction is 40 m or more and 200 m or less, and an area ratio of the second cathode region relative to a sum of areas of the first cathode region and the second cathode region is 0.1 or more and 0.8 or less.

A semiconductor device includes a gate extraction portion extracted from a gate electrode and extending from an active region to an outer peripheral region so as to be disposed above an end portion of a field insulating film. The end portion of the gate field insulating film above which the gate extraction portion is disposed is inclined in such a manner that a thickness of the field insulating film increases in a direction from the active region toward the outer peripheral region.