A semiconductor device includes a first transistor cell of a plurality of transistor cells of a vertical field effect transistor arrangement, and a second transistor cell of the plurality of transistor cells. The first transistor cell and the second transistor cell are electrically connected in parallel. A gate of the first transistor cell and a gate of the second transistor cell are controllable by different gate control signals.

An array substrate and a display panel are provided. The array substrate includes a transparent substrate including a display area and a rim area; a pixel structure and an antistatic switching tube which are arranged on a same side of the transparent substrate. The pixel structure includes a pixel thin-film transistor located in the display area, and the antistatic switching tube is located in the rim area. The pixel structure also includes first grounding wire located on a side of the antistatic switching tube facing away from the transparent substrate, and a second grounding wire located between the antistatic switching tube and the transparent substrate.

An apparatus includes an input/output (I/O) pin and an electrostatic discharge device. The electrostatic discharge device is coupled to the I/O pin and to a voltage regulator.

This invention involves a battery short-circuit protection circuit installed in a battery-load circuit. In the battery-load circuit, there is a battery and a load RL. The battery and RL form a circuit. The two ends of the battery are positive discharge end P+ and negative discharge end P, respectively. The battery short-circuit protection circuit is in series with the battery-load circuit. The battery short-circuit protection circuit includes a charge-discharge circuit, a current amplifier circuit, and a current comparator circuit. The charge-discharge circuit includes MOS transistors and a sampling resistor. The current amplifier circuit includes a signal conditioning circuit and a current amplifier. The current comparator circuit includes a current comparator, a current reference circuit for short-circuit protection consisting, a MOS transistor, a diode, a resistor, and an optronics relay.

According to an exemplary embodiment of the present disclosure, a display device includes a display panel divided into a display area, a non-display area, a bending area, and a pad area and bent in one direction in the bending area; a plurality of pixels disposed in the display area; at least one gate driver disposed in the non-display area and configured to supply a gate voltage to the plurality of pixels; flexible films connected to a plurality of pads disposed in the pad area; and at least one electrostatic discharge (ESD) circuit disposed in the pad area and connected to the at least one gate driver through a discharge line.

An integrated circuit is formed on a substrate containing a semiconductor material having a first conductivity type. A deep well having a second, opposite, conductivity type is formed in the semiconductor material of the first conductivity type. A deep isolation trench is formed in the substrate through the deep well so as separate an unused portion of the deep well from a functional portion of the deep well. The functional portion of the deep well contains an active circuit element of the integrated circuit. The separated portion of the deep well does not contain an active circuit element. A contact region having the second conductivity type and a higher average doping density than the deep well is formed in the separated portion of the deep well. The contact region is connected to a voltage terminal of the integrated circuit.

Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a body well region having a first conductivity type, a drift region and a source region each having a second conductivity type, where a channel portion of the body well region resides laterally between the source region and a first portion of the drift region that is adjacent to the channel portion. A gate structure overlies the channel portion and the adjacent portion of the drift region. A portion of the gate structure overlying the channel portion proximate the source region has the second conductivity type. Another portion of the gate structure that overlies the adjacent portion of the drift region has a different doping, and overlaps at least a portion of the channel portion, with the threshold voltage associated with the gate structure being influenced by the amount of overlap.

An ESD protection element can have a high ESD protection characteristic which has a desired breakdown voltage and flows a large discharge current. A junction diode is formed by an N+ type buried layer having a proper impurity concentration and a P+ type buried layer. The P+ type buried layer is combined with a P+ type drawing layer to penetrate an N type epitaxial layer and be connected to an anode element. An N+ type diffusion layer and a P+ typed diffusion layer connected to an surrounding the N+ type diffusion layer are formed in the N epitaxial layer surrounded by the P+ type buried layer etc. The N+ type diffusion layer and P+ type diffusion layer are connected to a cathode electrode. An ESD protection element is formed by the PN junction diode and a parasitic PNP bipolar transistor which uses the P+ type diffusion layer as an emitted, the N type epitaxial layer as the base, and the P+ type drawing layer etc. as the collector.

A display panel and a manufacturing method thereof are disclosed herein. The display panel includes a substrate, a peripheral circuit, a plurality of pixel electrodes, a plurality of switches, and an insulating layer. The substrate has a display region and a non-display region. At least a portion of the peripheral circuit is located on the display region of the substrate. The pixel electrodes are located on the display region of the substrate. The switches are respectively and electrically connected to the pixel electrodes, configured to be respectively switched on according to a plurality of scan signals, so as to transmit a plurality of data signals to the pixel electrodes. The insulating layer is located between the peripheral circuit and the pixel electrodes, and is configured to prevent the peripheral circuit from interfering with the pixel electrodes.

A circuit with a temperature detector includes a first FET and a second FET. Each of the first and second FETs has a channel structure having a non-planar structure. The second FET is in close proximity to the first FET. A gate of the second FET is separated from the first FET, and a source and drain of the second FET are shorted together. A resistance of the gate of the second FET between two terminals on the gate of the second FET varies with a temperature local to the first FET.