A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, a channel protective layer overlapping with a channel formation region of the first oxide semiconductor layer, and a pair of a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the channel protective layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved.

Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

Electronic devices employing thin-gate insulator transistors coupled to varactors to reduce gate-to-source/drain voltage to avoid voltage breakdown, and related fabrication methods. The electronic device includes thin-gate insulator transistors coupled in series to provide a single output node, and with their gates controlled by a single, input node to provide an effective three (3) terminal, single transistor device. The electronic device includes varactors each coupled in series between a respective gate of a thin-gate insulator transistor and the input node to support a single input signal for the electronic device. Each series coupled varactor and thin-gate insulator transistor are coupled to the input node in parallel to each other. Each varactor creates a voltage division between the input signal voltage and its series connected gate of a respective thin-gate insulator transistor to prevent the respective gate-to-source/drain voltage of the thin-gate insulator transistor from exceeding its breakdown voltage.

An integrated circuit includes a Schmitt trigger circuit. The Schmitt trigger circuit includes a first, second, third and fourth transistor, a first and second feedback transistor, and a first and second circuit. The first transistor is connected between a first node and a first voltage supply having a first supply voltage. The fourth transistor is connected between the third transistor and a second voltage supply having a second supply voltage. The first circuit is connected to a second node, the first and second voltage supply, and configured to supply the second supply voltage to the second node in response to being enabled. The second feedback transistor is connected to a third node, and a fourth node. The second circuit is connected to the fourth node, the first and second voltage supply, and configured to supply the first supply voltage to the fourth node in response to being enabled.

A semiconductor device includes a semiconductor body; a gate; a field plate, spaced from the gate, the field plate having a strip-like shape with main extensions along a first direction, the strip-like shape having a first and a second end opposite to one; a first conductive pad in electrical contact with the field plate at the first end through a first connecting region; a second conductive pad in electrical contact with the field plate at the second end through a second connecting region; and a third conductive pad in electrical contact with the field plate at the second end through a third connecting region. The conductive pads allow the use of the field plate as a temperature sensor.

A communication device including a substrate, a gate drive circuit, and a first tunable unit is provided. The gate drive circuit is disposed on the substrate. The gate drive circuit includes a first thin-film transistor and is configured to output a gate drive signal. The first tunable unit is disposed on the substrate and is electrically connected to the gate drive circuit. The first tunable unit includes a first drive circuit and a first tunable component. The first drive circuit includes a first terminal and a second terminal, and the first terminal of the first drive circuit is configured to receive the gate drive signal. The first tunable component is electrically connected to the second terminal of the first drive circuit.

A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, a channel protective layer overlapping with a channel formation region of the first oxide semiconductor layer, and a pair of a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the channel protective layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved.

According to one embodiment, a semiconductor device includes: a potential supply terminal to which a potential is supplied; a terminal (I/O terminal) for exchanging a signal with an outside; an I/O current detection load circuit electrically connected to the potential supply terminal and the terminal; and a current sensor circuit detecting the I/O current flowing through the I/O current detection load circuit. The current sensor circuit acquires a sensor current proportional to the I/O current and outputs the acquired sensor current as output information, and the I/O current is an abnormal current flowing through the I/O terminal due to at least one of electrostatic discharge and electromagnetic susceptibility and is a current that is greater than a predetermined current and that causes an abnormal state.

An electro-static discharge (ESD) protection apparatus is connected to a pin of a chip, and includes: an ESD protective semiconductor device including a drain electrode connected to the pin and a source electrode connected to a reference ground, and configured to discharge a current on the pin; and a comparator circuit, connected between the pin and a gate electrode of the ESD protective semiconductor device, and configured to: acquire a voltage on the pin to obtain a voltage signal, compare the voltage signal with a reference signal of a negative voltage, and control an on-state of the ESD protective semiconductor device according to a comparison result. When the voltage signal is less than the reference signal, a channel between the source electrode and the drain electrode of the ESD protective semiconductor device is opened by the comparator circuit.

A solid state switch, comprising a first metal-oxide-semiconductor field-effect transistor (MOSFET). The first MOSFET has a first terminal, a second terminal, a bulk terminal and a gate terminal, and is configured to be switched between an on-state and an off-state. The solid state switch also comprises a second MOSFET in series with the first MOSFET. The second MOSFET has a first terminal, a second terminal, a bulk terminal, and a gate terminal. The second terminal of the first MOSFET is connected to the second terminal of the second MOSFET. The solid state switch comprises a first buffer comprises an output terminal coupled to the bulk terminal of the first MOSFET, and an input terminal coupled to the first terminal of the first MOSFET.