The present invention discloses an electronic device using a group III nitride substrate fabricated via the ammonothermal method. By utilizing the high-electron concentration of ammonothermally grown substrates having the dislocation density less than 10.sup.5 cm.sup.2, combined with a high-purity active layer of Ga.sub.1-x-yAl.sub.xIn.sub.yN (0x1, 0y1) grown by a vapor phase method, the device can attain high level of breakdown voltage as well as low on-resistance. To realize a good matching between the ammonothermally grown substrate and the high-purity active layer, a transition layer is optionally introduced. The active layer is thicker than a depletion region created by a device structure in the active layer.

A semiconductor device includes a substrate having a main surface inclined in an off-direction from a {0001} surface, a semiconductor layer, and an epitaxial layer. The semiconductor layer includes a trench. Where an upstream side is an off-angle upstream side and a downstream side is an off-angle downstream side in a direction with the off-direction projected on the main surface of the substrate, a side wall of the trench includes first and second side wall portions facing each other and each crossing the off-direction of the substrate. The first side wall portion is situated closer to the off-angle upstream side than the second side wall portion.

A semiconductor device includes a first n type layer and a second n type layer that are sequentially disposed on a first surface of an n+ type silicon carbide substrate; a first trench and a second trench that are disposed at the second n type layer and are spaced apart from each other; a p type region surrounding a lateral surface and a lower surface of the first trench; an n+ type region disposed on the p type region and the second n type layer; a gate insulating layer disposed in the second trench; a gate electrode disposed on the gate insulating layer; an oxide layer disposed on the gate electrode; a source electrode disposed on the oxide layer and the n+ type region disposed in the first trench; and a drain electrode disposed at a second surface of the n+ type silicon carbide substrate.

A semiconductor device includes an n type layer disposed in a first surface of an n+ type silicon carbide substrate, a first trench and a second trench disposed in the n type layer and spaced apart from each other, a p type region surrounding a lateral surface and a corner of the first trench, an n+ type region disposed on the p type region and the n type layer between the first trench and the second trench, a gate insulating layer disposed in the second trench, a gate electrode disposed on the gate insulating layer, an oxide layer disposed on the gate electrode, a source electrode disposed on the oxide layer and the n+ type region, and disposed in the first trench, and a drain electrode disposed in a second surface of the n+ type silicon carbide substrate, wherein the source electrode contacts the n type layer.

Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.

The present invention discloses a method of forming a high voltage junctionless device with drift region. The drift region formed between the semiconductor channel and the dielectric layer enables the high voltage junctionless device to exhibit higher punch-through voltages and high mobility with better performance and reliability.

A vertical transistor and the fabrication method. The transistor comprises a first surface and a second surface that is opposite to the first surface. A drift region of the first doping type, this drift region is located between the first surface and the second surface; at least one source region of the first doping type and the source region being located between the drift region and the first surface, with a first dielectric layer located between adjacent source regions; at least one drain region with said first doping type and said drain region being located between said drift region and said second surface, a gate being provided between adjacent drain regions. Said gate includes a gate electrode and a gate dielectric layer disposed between said gate electrode and said drift region, and the second dielectric layer being positioned between said gate electrode and said second surface.

In the silicon carbide semiconductor element, a second silicon carbide semiconductor layer that is in contact with the surface of a first silicon carbide semiconductor layer has at least an upper layer including a dopant of a first conductivity type at a high concentration. Above a junction field effect transistor (JFET) region interposed between body regions that are disposed in the first silicon carbide semiconductor layer so as to be spaced from each other, the silicon carbide semiconductor element has a channel removed region, which is a cutout formed by removing a high concentration layer from the front surface side of the second silicon carbide semiconductor layer, the high concentration layer having a higher dopant concentration than at least the dopant concentration of the JFET region. The width of the channel removed region is smaller than that of the JFET region.

A semiconductor device may include a semiconductor layer having a first conductivity type, a well region of a second conductivity type in the semiconductor layer wherein the first and second conductivity types are different, and a terminal region of the first conductivity type in the well region. An epitaxial semiconductor layer may be on the surface of the semiconductor layer including the well region and the terminal region with the epitaxial semiconductor layer having the first conductivity type across the well and terminal regions. A gate electrode may be on the epitaxial semiconductor layer so that the epitaxial semiconductor layer is between the gate electrode and portions of the well region surrounding the terminal region at the surface of the semiconductor layer.

Vertical field effect transistor (FET) device with tunable bandgap source/drain regions are provided, as well as methods for fabricating such vertical FET devices. For example, a vertical FET device includes a lower source/drain region formed on a substrate, a vertical semiconductor fin formed on the lower source/drain region, and an upper source/drain region formed on an upper region of the vertical semiconductor fin. The lower source/drain region and vertical semiconductor fin are formed of a first type of III-V semiconductor material. The upper source/drain region is formed of a second type of III-V semiconductor material which comprises the first type of III-V semiconductor material and at least one additional element that increases a bandgap of the second type of III-V semiconductor material of the upper source/drain region relative to a bandgap of the first type of III-V compound semiconductor material of the lower source/drain region and the vertical semiconductor fin.