The present disclosure provides a gallium oxide semiconductor structure, a vertical gallium oxide-based power device, and a preparation method. An unintentionally doped gallium oxide layer (110) is transferred to a highly doped and highly thermally conductive heterogeneous substrate (200) by bonding and thinning; then a heavily doped gallium oxide layer (120) is formed on the gallium oxide layer by treating and ion implantation, thereby preparing the gallium oxide semiconductor structure including the heterogeneous substrate (200), the gallium oxide layer (110), and the heavily doped gallium oxide layer (120) stacked in sequence. In the vertical gallium oxide-based power device prepared on the basis of the gallium oxide semiconductor structure, the gallium oxide layer (110) is a thicker intermediate layer and a carrier concentration of the gallium oxide layer (110) is less than that of the heavily doped gallium oxide layer (120). Therefore, the breakdown voltage of the device is also increased through structural design. The highly thermally conductive heterogeneous substrate (200) improves the heat dissipation performance of the device. The device with multiple Fin structures provides a large amount of current.

A semiconductor device for high power consumption is provided. The semiconductor device includes a substrate, a first conductor over the substrate, a first metal oxide over the first conductor, a first oxide over the first metal oxide, a second oxide over the first oxide, a first insulator over the second oxide, a second conductor over the first insulator, a second insulator over the second conductor, a third insulator in contact with a side surface of the second conductor, a side surface of the first insulator, and a side surface of the second insulator, a second metal oxide over the second oxide, the second insulator, and the third insulator, and a third conductor over the second metal oxide. The second conductor includes a region overlapping with the second oxide. The third conductor includes a region in contact with the second metal oxide. The second metal oxide includes a region in contact with the second oxide. The carrier concentration of the second oxide is lower than the carrier concentration the first oxide.

A power semiconductor device includes an SiC semiconductor layer, a plurality of well regions disposed in the semiconductor layer such that two adjacent well regions at least partially make contact with each other, a plurality of source regions on the plurality of well regions in the semiconductor layer, a drift region in a first conductive type, a plurality of trenches recessed into the semiconductor layer from the surface of the semiconductor layer, a gate insulating layer on an inner wall of each trench, a gate electrode layer disposed on the gate insulating layer and including a first part disposed in each trench and a second part on the semiconductor layer, and a pillar region positioned under the plurality of well regions to make contact with the drift region and the plurality of well regions in the semiconductor layer, and having a second conductive type.

The present disclosure relates to a manufacturing method for a power semiconductor device (1, 40), comprising: forming multiple growth templates on a carrier substrate (2), comprising at least a first plurality of hollow growth templates (18) and a second plurality of hollow growth templates (28); selectively growing a first sequence of differently doped wide bandgap semiconductor materials in each one of the first hollow growth templates (18), thereby forming a corresponding plurality of first semiconductor structures (5) of a first type, in particular n+/p/n/n+ structures; and selectively growing a second sequence of differently doped wide bandgap semiconductor materials in each one of the second hollow growth templates (28), thereby forming a corresponding plurality of second semiconductor structures (6) of a second type, in particular n+/n/p/n+ structures. The disclosure further relates to a power semiconductor device (1, 40) comprising a carrier substrate (2), at least one dielectric layer (4, 27, 31), a plurality of first semiconductor structures (5) of a first type, and a plurality of second semiconductor structures (6) of a second type formed within the at least one dielectric layer (4, 27, 31).

A process of forming an electronic device can form an accumulation channel or an integrated diode by selective doping parts of a workpiece. In an embodiment, a doped region can be formed by implanting a sidewall of a body region. In another embodiment, a doped region can correspond to a remaining portion of a semiconductor layer after forming another doped region by implanting into a contact opening. The accumulation channel or the integrated diode can lower the barrier for a body diode turn-on. Reduced stored charge and Q.sub.RR may be achieved, leading to lower switching losses.

A MOSFET device based on nickel oxide (NiO) gate modulation and its preparation method are provided. The MOSFET device includes a substrate layer, a first N-type gallium nitride (GaN) layer, a second N-type GaN layer, a P-type GaN layer, and a third N-type GaN layer disposed sequentially from bottom to top; gate stepped parts extending from both ends of an upper surface of the third N-type GaN layer to an interior of the second N-type GaN layer; gate structures extending from the upper surface of the third N-type GaN layer to bottoms of the gate stepped parts; a source recess, a source electrode, drain electrodes and NiO modulation layers extending from the bottoms of the gate stepped parts to an upper surface of the first N-type GaN layer. By setting the NiO modulation layers, a voltage withstand level of the MOSFET device is improved.

A power semiconductor device includes an SiC semiconductor layer, a plurality of well regions disposed in the semiconductor layer such that two adjacent well regions at least partially make contact with each other, a plurality of source regions on the plurality of well regions in the semiconductor layer, a drift region in a first conductive type, a plurality of trenches recessed into the semiconductor layer from the surface of the semiconductor layer, a gate insulating layer on an inner wall of each trench, a gate electrode layer disposed on the gate insulating layer and including a first part disposed in each trench and a second part on the semiconductor layer, and a pillar region positioned under the plurality of well regions to make contact with the drift region and the plurality of well regions in the semiconductor layer, and having a second conductive type.

A semiconductor structure includes a Schottky diode structure, which includes: a first trench extending through a first N-type semiconductor layer and being disposed in the first N-type semiconductor layer; a first insulating layer disposed in the first trench; two polysilicon layers or metal silicide layers disposed in the first trench, wherein an upper one and a lower one of the polysilicon layers or metal silicide layers are disposed in parallel; a first P-type protective layer, which is grounded and disposed on a bottom of the first trench, and contacts the first insulating layer and a bottom surface of the lower one of the polysilicon layers or metal silicide layers; a metal layer respectively disposed as a top surface and a lower bottom surface of the semiconductor structure to form a source and a drain as electrodes for the semiconductor structure to be connected to an external device.