In a general aspect, an apparatus can include a silicon carbide (SiC) trench gate MOSFET with improved operation due, at least in part, to a reduced gate capacitance. In the SiC trench gate MOSFET, a thick gate oxide can be formed on a bottom surface of the gate trench and a built-in channel, having a vertical portion and a lateral portion, can be formed to electrically connect a vertical inversion-layer channel, such as in a channel stopper layer, to a vertical JFET channel region and a drift region.

A base layer is used that has an N-type SiC layer formed in a surface layer on the front surface side of an N-type SiC substrate, and a P-type region is formed on a surface of the N-type SiC layer with an N-type source region selectively formed in a surface layer of the P-type region. A source electrode is formed on a surface of the N-type source region and a drain electrode is formed on the back surface side of the N-type SiC substrate. Additionally, the gate electrode is formed via a gate insulation film only on a surface of the P-type region. In this way, high electric field is no longer applied to the gate insulation film on the surface of the N-type SiC layer due to stoppage of voltage application to the gate electrode.

Examples include a field effect transistor (FET) including a stack that includes a III-nitride semiconductor. The stack includes a drain layer, a drift layer, a body layer, and a source layer. The FET includes an n-doped region of the III-nitride semiconductor extending from the drift layer into a first part of the body layer. A height in the stack of a top surface of the n-doped region is located below a height in the stack of a top of the body layer. A trench extends from a top surface of the stack through the source layer and an upper part of the body layer. The upper part is adjacent to the first part. The FET includes a gate dielectric covering surfaces of the trench and a gate electrode over the gate dielectric. A bottom surface of the gate dielectric is in contact with the top surface of the n-doped region.

Semiconductor devices, and more particularly semiconductor devices with improved edge termination structures are disclosed. A semiconductor device includes a drift region that forms part of an active region. An edge termination region is arranged along a perimeter of the active region and also includes a portion of the drift region. The edge termination region includes one or more sub-regions of an opposite doping type than the drift region and one or more electrodes may be capacitively coupled to the drift region by way of the one or more sub-regions. During a forward blocking mode for the semiconductor device, the one or more electrodes may provide a path that draws ions away from passivation layers that are on the edge termination region and away from the active region. In this manner, the semiconductor device may exhibit reduced leakage, particularly at higher operating voltages and higher associated operating temperatures.

In the present invention, in a FinFET having a channel forming region on a surface of a fin that is a semiconductor layer protruding on an upper surface of a substrate, a channel at a corner of the fin is prevented from becoming an ON state with a low voltage and a steep ON/OFF operation is made possible. As a means thereof, in a MOSFET that has a plurality of trenches, each of which have embedded therein a gate electrode, on an upper surface of an n-type epitaxial substrate provided with a drain region on a bottom surface and that has a channel region formed on a surface of a fin which is a protrusion part between the trenches adjacent to each other, a p-type body layer that constitutes a lateral surface of the fin, and a p.sup.+-type semiconductor region that constitutes a corner which is an end of the upper surface of the fin, are formed.

A device having reduced Rds(on) is described. The device comprises a unit cell. The unit cell comprises: a first region, a second region, a third region, and a fourth region. The fourth region is residing on the first region, the second region, and the third region. The second region connects the first region and the third region. The first region, the second region and the third region are of same conductivity type (e.g., second conductivity type). In an embodiment, the fourth region comprises a fifth region and a sixth region. The fourth region, the fifth region, and the sixth region are of same conductivity type (e.g., first conductivity type). The fourth region is on the first region. The fifth region is on the second region. The sixth region is on the third region. In an embodiment, the device achieves reduced Rds(on) by relaxing the JFET constraint.

A power semiconductor device comprises a semiconductor body with a top side, and a main electrode and an adjacent gate electrode thereon. The semiconductor body comprises a drift layer of a first conductivity type, a base region of a second conductivity type between the drift layer and the top side, a contact region of the first conductivity type between the drift layer and the top side. The contact region adjoins the base region and the top side. The semiconductor body comprises a drift region of the first conductivity type arranged next to and adjoining the base region. The main electrode is in electrical contact with the contact region. The gate electrode at least partially covers a channel portion of the base region, which lies between the contact region and the drift region. At least one of the contact region and the drift region projects beyond the base region.

In a semiconductor device, a first deep layer has a high-concentration region and a low-concentration region in a concentration profile of an impurity concentration along a depth direction. The high-concentration region has a high concentration peak at which an impurity concentration is maximum, and includes a region that is not depleted in an off state. The low-concentration region is closer to a high-concentration layer than the high-concentration region, has a region in which a gradient of change in impurity concentration is smaller than a predetermined value, and is depleted in the off state. A first length between a first position closest to a base layer in the first deep layer and a second position of the high concentration peak is shorter than a second length between the second position and a third position closest to the base layer in the low-concentration region.

A super junction semiconductor device includes a substrate; a plurality of epitaxial layers disposed on the substrate; an active region disposed on one region of the substrate and the epitaxial layer; a peripheral region and an edge termination region surrounding the active region; and a plurality of first conductive type pillar regions and a plurality of second conductive type pillar regions disposed in the plurality of epitaxial layers, respectively. Each of the plurality of first conductive type pillar regions and the plurality of second conductive type pillar regions in the active region is divided into a lower pillar region, an intermediate pillar region, and an upper pillar region, sequentially. A dopant concentration gradually increases from the lower pillar region to the intermediate pillar region, and another dopant concentration gradually decreases from the intermediate pillar region to the upper pillar region.

A power semiconductor device comprises a semiconductor body with a top side, and a main electrode and an adjacent gate electrode thereon. The semiconductor body comprises a drift layer of a first conductivity type, a base region of a second conductivity type between the drift layer and the top side, a contact region of the first conductivity type between the drift layer and the top side. The contact region adjoins the base region and the top side. The semiconductor body comprises a drift region of the first conductivity type arranged next to and adjoining the base region. The main electrode is in electrical contact with the contact region. The gate electrode at least partially covers a channel portion of the base region, which lies between the contact region and the drift region. At least one of the contact region and the drift region projects beyond the base region.