H10F71/1274

Radiation and temperature hard multi-pixel avalanche photodiodes

The structure and method of fabricating a radiation and temperature hard avalanche photodiode with integrated radiation and temperature hard readout circuit, comprising a substrate, an avalanche region, an absorption region, and a plurality of Ohmic contacts are presented. The present disclosure provides for tuning of spectral sensitivity and high device efficiency, resulting in photon counting capability with decreased crosstalk and reduced dark current.

Electronic devices comprising n-type and p-type superlattices
09685587 · 2017-06-20 · ·

A superlattice and method for forming that superlattice are disclosed. In particular, an engineered layered single crystal structure forming a superlattice is disclosed. The superlattice provides p-type or n-type conductivity, and comprises alternating host layers and impurity layers, wherein: the host layers consist essentially of a semiconductor material; and the impurity layers consist essentially of a corresponding donor or acceptor material.

Methods for Producing Composite GaN Nanocolumns and Light Emitting Structures Made from the Methods

A method for growing on a substrate strongly aligned uniform cross-section semiconductor composite nanocolumns is disclosed. The method includes: (a) forming faceted pyramidal pits on the substrate surface; (b) initiating nucleation on the facets of the pits; and; (c) promoting the growth of nuclei toward the center of the pits where they coalesce with twinning and grow afterwards together as composite nanocolumns. Multi-quantum-well, core-shell nanocolumn heterostructures can be grown on the sidewalls of the nanocolumns. Furthermore, a continuous semiconductor epitaxial layer can be formed through the overgrowth of the nanocolumns to facilitate fabrication of high-quality planar device structures or for light emitting structures.

III-V solar cell structure with multi-layer back surface field

Photovoltaic devices including direct gap III-V absorber materials and operatively associated back structures enhance efficiency by enabling photon recycling. The back structures of the photovoltaic devices include wide bandgap III-V layers, highly doped (In)GaAs layers, patterned oxide layers and metal reflectors that directly contact the highly doped (In)GaAs layers through vias formed in the back structures. Localized ohmic contacts are formed in the back structures of the devices.

Light Extraction from Optoelectronic Device

An optoelectronic device configured for improved light extraction through a region of the device other than the substrate is described. A group III nitride semiconductor layer of a first polarity is located on the substrate and an active region can be located on the group III nitride semiconductor layer. A group III nitride semiconductor layer of a second polarity, different from the first polarity, can located adjacent to the active region. A first contact can directly contact the group III nitride semiconductor layer of the first polarity and a second contact can directly contact the group III nitride semiconductor layer of the second polarity. Each of the first and second contacts can include a plurality of openings extending entirely there through and the first and second contacts can form a photonic crystal structure. Some or all of the group III nitride semiconductor layers can be located in nanostructures.

Optoelectronic Device with a Nanowire Semiconductor Layer

A heterostructure for use in an electronic or optoelectronic device is provided. The heterostructure includes one or more semiconductor layers containing columnar nanostructures (e.g., nanowires). The nanowire semiconductor layer can include sub-layers of varying composition, at least one of which is an active layer that can include quantum wells and barriers. A heterostructure can include n-type and p-type semiconductor contact layers adjacent to the nanowire semiconductor layer containing the active layer.

LATTICE MATCHABLE ALLOY FOR SOLAR CELLS

An alloy composition for a subcell of a solar cell is provided that has a bandgap of at least 0.9 eV, namely, Ga.sub.1-xIn.sub.xN.sub.yAs.sub.1-y-zSb.sub.z with a low antimony (Sb) content and with enhanced indium (In) content and enhanced nitrogen (N) content, achieving substantial lattice matching to GaAs and Ge substrates and providing both high short circuit currents and high open circuit voltages in GaInNAsSb subcells for multijunction solar cells. The composition ranges for Ga.sub.1-xIn.sub.xN.sub.yAs.sub.1-y-zSb.sub.z are 0.07x0.18, 0.025y0.04 and 0.001z0.03.

Method for etching multi-layer epitaxial material

A single-step wet etch process is provided to isolate multijunction solar cells on semiconductor substrates, wherein the wet etch chemistry removes semiconductor materials nonselectively without a major difference in etch rate between different heteroepitaxial layers. The solar cells thus formed comprise multiple heterogeneous semiconductor layers epitaxially grown on the semiconductor substrate.

Contact Configuration for Optoelectronic Device

An optoelectronic device with a multi-layer contact is described. The optoelectronic device can include a n-type semiconductor layer having a surface. A mesa can be located over a first portion of the surface of the n-type semiconductor layer and have a mesa boundary. A n-type contact region can be located over a second portion of the surface of the n-type semiconductor contact layer entirely distinct from the first portion, and be at least partially defined by the mesa boundary. A first n-type metallic contact layer can be located over at least a portion of the n-type contact region in proximity of the mesa boundary, where the first n-type metallic contact layer forms an ohmic contact with the n-type semiconductor layer. A second n-type metallic contact layer can be located over a second portion of the n-type contact region, where the second n-type metallic contact layer is formed of a reflective metallic material.

ELECTRONIC DEVICES WITH NANORINGS, AND METHODS OF MANUFACTURE THEREOF
20170084786 · 2017-03-23 ·

Systems and methods for electronic devices are presented. A device includes a substrate. An Indium Gallium Nitride (InGaN) nanoring is formed over the substrate. The InGaN nanoring includes an alloy of Indium Nitride (InN) and Gallium Nitride (GaN). The alloy includes at least 6 percent Indium. A GaN layer may be formed over the InGaN nanoring, and a first electrode is formed over the GaN layer. In one embodiment, the alloy includes less than about 70 percent Indium.