A method of forming a semiconductor device is provided. The method includes forming an etch stop layer on a substrate having a first thickness, forming an epitaxial layer on the etch stop layer, and forming a wafer device on the epitaxial layer. The wafer device is bonded to a bonding wafer using hybrid bonding. The substrate is then ground to a second thickness less than the first thickness and planarized to a third thickness less than the second thickness. A mask layer is deposited on a bottom surface of the etch stop layer, and at least one via opening is formed in the mask layer. The etch stop layer is selectively removed, and the mask layer is removed to expose the substrate at the third thickness.

A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

Techniques are provided herein to form semiconductor devices having strained channel regions. In an example, semiconductor nanoribbons of silicon germanium (SiGe) or germanium tin (GeSn) may be formed and subsequently annealed to drive the germanium or tin inwards along a portion of the semiconductor nanoribbons thus increasing the germanium or tin concentration through a central portion along the lengths of the one or more nanoribbons. Specifically, a nanoribbon may have a first region at one end of the nanoribbon having a first germanium concentration, a second region at the other end of the nanoribbon having substantially the same first germanium concentration (e.g., within 5%), and a third region between the first and second regions having a second germanium concentration higher than the first concentration. A similar material gradient may also be created using tin. The change in material composition (gradient) along the nanoribbon length imparts a compressive strain.

A semiconductor memory device comprises: a laterally oriented hybrid channel including outer channel materials and an inner channel material interposed between the outer channel materials; a laterally oriented double word line with the hybrid channel interposed therebetween; a vertically oriented bit line connected to a first end of the hybrid channel; and a capacitor connected to a second end of the hybrid channel.

The present application discloses a method for manufacturing a source/drain epitaxial layer of an FDSOI MOSFET, comprising: step 1, forming a shallow trench isolation on an FDSOI substrate; step 2, opening a formation region of a source/drain region of the MOSFET; step 3, performing first epitaxial growth to form a first pure silicon epitaxial layer; step 4, performing a first etching process to remove polysilicon particles generated from step 3; and step 5, performing epitaxial growth to sequentially form a second source/drain epitaxial seed layer, a third source/drain epitaxial bulk layer, and a fourth source/drain epitaxial cap layer on a surface of the first pure silicon epitaxial layer, so the four epitaxial layers are stacked to form the source/drain epitaxial layer.

Semiconductor devices and methods of manufacturing the same are described. The method includes forming a bottom dielectric isolation (BDI) layer on a substrate and depositing a template material in the source/drain trench. The template material is crystallized. Epitaxially growth of the source and drain regions then proceeds, which growth advantageously occurring on the bottom and sidewalls of the source and drain regions.

Semiconductor devices and methods of manufacturing the same are described. Transistors are fabricated using a standard process flow. A via opening extending from the top surface of the substrate to a bottom surface of the wafer device is formed, thus allowing nano TSV for high density packaging, as well as connecting the device to the backside power rail. A metal is deposited in the via opening, and the bottom surface of the wafer device is bound to a bonding wafer. The substrate is optionally thinned, and a contact electrically connected to the metal is formed.

Techniques for forming thin film transistors (TFTs) having multilayer and/or concentration gradient semiconductor regions. An example integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, and a semiconductor region on the gate dielectric. In some cases, the semiconductor region includes a plurality of compositionally different material layers, at least two layers of the different material layers each being a semiconductor layer. In some other cases, the semiconductor region includes a single layer having a material concentration gradient extending from a bottom surface of the single layer (adjacent to the gate dielectric) to a top surface of the single layer. The integrated circuit further includes first and second conductive contacts that each contact a respective portion of the semiconductor region. One example application of the techniques is with respect to forming backend (within the interconnect region) memory structures configured with multilayer and/or concentration gradient TFTs.