A chip includes a semiconductor substrate, an electrical connector over the semiconductor substrate, and a molding compound molding a lower part of the electrical connector therein. A top surface of the molding compound is lower than a top end of the electrical connector. A recess extends from the top surface of the molding compound into the molding compound.

A manufacturing method for a semiconductor chip includes: preparing a GaN wafer; producing a processed wafer by forming an epitaxial film on a surface of the GaN wafer to have chip formation regions adjacent to a first surface of the processed wafer; forming a first surface-side element component of a semiconductor element in each chip formation region; forming a wafer transformation layer along a planar direction of the processed wafer by irradiating an inside of the processed wafer with a laser beam; dividing the processed wafer at the wafer transformation layer into a chip formation wafer and a recycle wafer; extracting a semiconductor chip from the chip formation wafer; and after the preparing the GaN wafer and before the dividing the processed wafer, irradiating an inside of the gallium nitride wafer or the processed wafer with a laser beam to form a mark by deposition of gallium.

A method of manufacturing a semiconductor device includes forming a separation trench into a first main surface of a semiconductor substrate and removing substrate material from a second main surface of the semiconductor substrate, so as to thin the substrate to a thickness of less than 100 m, the second main surface being opposite to the first main surface, so as to uncover a bottom side of the trench. Additional methods of manufacturing semiconductor devices are provided.

According to various embodiments, a method for manufacturing a semiconductor device may include providing a semiconductor workpiece including a device region at a first side of the semiconductor workpiece, wherein a mechanical stability of the semiconductor workpiece is insufficient to resist at least one back end process without damage, and depositing at least one conductive layer over a second side of the semiconductor workpiece opposite the first side of the semiconductor workpiece, wherein the at least one conductive layer increases the mechanical stability of the semiconductor workpiece to be sufficient to resist the at least one back end process without damage.

A wafer is formed with a plurality of division lines on a front surface of a single crystal substrate having an off angle and formed with devices in a plurality of regions partitioned by the division lines. The wafer is processed by setting a numerical aperture (NA) of a focusing lens for focusing a pulsed laser beam so that a value obtained by dividing the numerical aperture (NA) by a refractive index (N) of the single crystal substrate falls within the range from 0.05 to 0.2. The pulsed laser beam is applied along the division lines, with a focal point of the pulsed laser beam positioned at a desired position from a back surface of the single crystal substrate, so as to form shield tunnels each composed of a pore and a pore-shielding amorphous portion along the division lines from the focal point positioned inside the single crystal substrate.

A substrate dividing method includes preparing a substrate that is formed with division start points along streets and that has a protective sheet attached to a surface on one side thereof and rolling a roller on a surface on the other side of the substrate, to attach an expanding tape. Next, suction by a holding table is cancelled, and, in a state in which a slight gap is formed between a holding surface of the holding table and the protective sheet, the roller is brought into contact with the expanding tape and rolled, thereby extending cracks extending from the division start points while causing the substrate to sink into the gap through the protective sheet with the division start points as starting points, and the expanding tape is expanded to widen the chip intervals with the division start points as starting points.

Techniques are described for the use of moats for isolating and singulating semiconductor devices formed on a wafer. Described techniques use dielectric films, such as an oxide-nitride film, to coat moat surfaces and provide passivation. The dielectric films may form a junction with a metal contact layer, to reduce electrical overstress that may otherwise occur in the resulting semiconductor devices. To ensure coverage of the moat surfaces, spray coating of a positive photoresist may be used.

A system and method for connecting semiconductor dies is provided. An embodiment comprises connecting a first semiconductor die with a first width to a second semiconductor die with a larger second width and that is still connected to a semiconductor wafer. The first semiconductor die is encapsulated after it is connected, and the encapsulant and first semiconductor die are thinned to expose a through substrate via within the first semiconductor die. The second semiconductor die is singulated from the semiconductor wafer, and the combined first semiconductor die and second semiconductor die are then connected to another substrate.

A chip includes a semiconductor substrate, an electrical connector over the semiconductor substrate, and a molding compound molding a lower part of the electrical connector therein. A top surface of the molding compound is lower than a top end of the electrical connector. A recess extends from the top surface of the molding compound into the molding compound.

Provided is a sheet for workpiece processing that includes a base material and a pressure sensitive adhesive layer laminated on one side of the base material. The pressure sensitive adhesive layer is composed of an active energy ray-curable pressure sensitive adhesive that contains a hindered amine-based stabilizer. Such a sheet for workpiece processing enables easy separation of workpieces even when a heating treatment is performed.