A junction field-effect transistor (JFET) with a gate region that includes two separate sub-regions having material of different conductivity types and/or a Schottky junction that substantially suppresses gate current when the gate junction is forward-biased, as well as complementary circuits that incorporate such JFET devices.

A substrate includes a support structure comprising a polycrystalline ceramic core, a first adhesion layer encapsulating the polycrystalline ceramic core, a barrier layer encapsulating the first adhesion layer, a second adhesion layer coupled to the barrier layer, and a conductive layer coupled to the second adhesion layer. The substrate also includes a bonding layer coupled to the support structure, a substantially single crystal silicon layer coupled to the bonding layer, and an epitaxial semiconductor layer coupled to the substantially single crystal silicon layer.

A semiconductor device includes a semiconductor substrate with an upper surface and a channel, source and drain electrodes over the upper surface of the semiconductor substrate, a passivation layer between the source and drain electrodes, a first dielectric layer over the passivation layer, a gate electrode between the source and drain electrodes, and a conductive field plate adjacent to the gate electrode. The passivation layer includes a lower passivation sub-layer and an upper passivation sub-layer over the lower passivation sub-layer. The gate electrode includes a lower portion that extends through the passivation layer. The conductive field plate includes a first portion with a recessed region that extends through the upper passivation sub-layer but does not extend through the lower passivation sub-layer, and an overhanging portion that extends over an upper surface of the first dielectric layer.

A semiconductor device includes a drift layer including silicon carbide and having a first conductivity type, a channel layer on the drift layer, the channel layer including silicon carbide and having the first conductivity type, and a source layer on the channel layer, the source layer including silicon carbide and having the first conductivity type. The device includes first and second trenches extending through the source layer and at least partially into the channel layer. The first and second trenches define a mesa therebetween having a mesa sidewall adjacent the channel layer. A heterojunction layer is in the first trench. The heterojunction layer includes a semiconductor material having a second conductivity type opposite the first conductivity type, wherein the heterojunction layer forms a PN heterojunction with silicon carbide.

A vertical junction field effect transistor includes a trench structure laterally arranged between mesa regions along a first lateral direction. The trench structure extends into a semiconductor body from a first surface of the semiconductor body. Each of the mesa regions includes a mesa channel region of a first conductivity type. The vertical junction field effect transistor further includes a gate region of a second conductivity type. The gate region adjoins at least part of opposite sidewalls of the trench structure and to a bottom side of the trench structure. The trench structure includes a silicon layer adjoining the gate region at the bottom side of the trench structure. A first thickness of the gate region at the bottom side of the trench structure is larger than a second thickness of the gate region at each of the opposite sidewalls of the trench structure.

A method includes forming a semiconductor device that includes a semiconductor substrate with an upper surface and a channel, source and drain electrodes over the upper surface of the semiconductor substrate, a passivation layer between the source and drain electrodes, a first dielectric layer over the passivation layer, a gate electrode between the source and drain electrodes, and a conductive field plate adjacent to the gate electrode. The passivation layer includes a lower passivation sub-layer and an upper passivation sub-layer over the lower passivation sub-layer. The gate electrode includes a lower portion that extends through the passivation layer. The conductive field plate includes a first portion with a recessed region that extends through the upper passivation sub-layer but does not extend through the lower passivation sub-layer, and an overhanging portion that extends over an upper surface of the first dielectric layer.