To provide a quantum device capable of preventing a connection member connecting a quantum chip with an interposer from being broken. The quantum device 1 includes at least one quantum chip 10, at least one interposer 20 on which the at least one quantum chip 10 is mounted, and a plurality of connection members 30 formed of a conductor. The plurality of connection members 30 are disposed between the quantum chip 10 and the interposer 20, and connect the quantum chip 10 with the interposer 20. The size of the connection member 30 on the surface along the mounting surface 20s of the interposer 20 is changed according to the position thereof relative to the quantum chip 10.

A quantum device capable of effectively cooling a quantum chip and an area (e.g., a space) therearound is provided. A quantum device 1 includes a quantum chip 10 and an interposer 20 on which the quantum chip 10 is located. The interposer 20 includes an interposer substrate 22 and an interposer wiring layer 30. The interposer wiring layer 30 is disposed on a surface 22a of the interposer substrate 22 on a side on which the quantum chip 10 is located. The interposer wiring layer 30 includes, in at least a part thereof, a superconducting material layer 32 formed of a superconducting material and a non-superconducting material layer 34 formed of a non-superconducting material.

A quantum device (100) includes: an interposer (112); a quantum chip (111); a first connection part (130) that is provided between the interposer (112) and the quantum chip (111) and electrically connects a wiring layer of the interposer (112) to a wiring layer of the quantum chip (111); and a second connection part (140) that is provided on a main surface of the interposer (112) where the first connection part (130) is arranged and is connected to a cooling plate (115).

A quantum device (100) includes: an interposer (112); a quantum chip (111); and a connection part (130) that is provided between the interposer (112) and the quantum chip (111) and electrically connects a wiring layer of the interposer (112) to a wiring layer of the quantum chip (111), in which the connection part (130) includes: a plurality of pillars (131) arranged on a main surface of the interposer (112); and a metal film (132) provided on a surface of the plurality of pillars (131) in such a way that it contacts the wiring layer of the quantum chip (111) and the thickness of the metal film at outer peripheral parts of the tip of each of the plurality of pillars (131) becomes larger than the thickness of the metal film at a center part of the tip of each of the plurality of pillars (131).

A quantum device capable of securing terminals for external connection is provided. A quantum device according to an example embodiment includes a quantum chip 10, an interposer 20 on which the quantum chip 10 is mounted, and a socket 40 disposed so as to be opposed to the interposer 20, the socket 40 comprising a movable pin 47 and a housing 45 supporting the movable pin 47, in which at least one end of the movable pin 47, which includes the one end and the other end opposite to the one end, is movable relative to the housing 45, the one end being in electrical contact with a terminal of the interposer 20, and the other end is in an electrical contact with a terminal of a board 50 on which a connector 51 is formed, the connector 51 being configured to serve as an external input/output.

In an embodiment, a quantum device includes an interposer layer comprising a set of vias. In an embodiment, the quantum device includes a dielectric layer formed on a first side of the interposer, the dielectric layer including a set of transmission lines communicatively coupled to the set of vias. In an embodiment, the quantum device includes a plurality of qubit chips coupled to an opposite side of the interposer layer, each qubit chip of the plurality of qubit chips including: a plurality of qubits on a first side of the qubit chip and a plurality of protrusions on a second side of the qubit chip. In an embodiment, the quantum device includes a heat sink thermally coupled with the plurality of qubit chips, the heat sink comprising a plurality of recesses aligned with the plurality of protrusions of the plurality of qubit chips.

Techniques for creating an offset embedded ground plane cutout for a qubit device to facilitate frequency tuning of the qubit device are presented. A qubit device can comprise a first substrate and second substrate in a flip-chip assembly. The qubit chip assembly can comprise a qubit component fabricated on the first substrate. The qubit component can comprise a Josephson junction (JJ) circuit that can be offset from a center point of the qubit component. The qubit chip assembly can comprise an embedded ground plane situated on a surface of the qubit chip assembly. A cutout section can be formed in the ground plane and positioned over the JJ circuit. The cutout section can enable access of an optical signal or magnetic flux to the JJ circuit. A frequency of the qubit component can be tuned based on application of the optical signal or magnetic flux to the JJ circuit.

A quantum semiconductor device includes a qubit chip; an interposer chip, with a handler, including a through-silicon-via (TSV) coupled to a first side of the qubit chip. A multi-level wiring (MLW) layer contacts an underside of the interposer chip and coupling to the top side of the handler, the TSV facilitates an electrical signal connection between the MLW layer, a topside of the interposer chip and the qubit chip, wherein structure of the device mitigates signal cross-talk across respective lines of the MLW layer.

A device includes a first substrate formed of a first material that exhibits a threshold level of thermal conductivity. The threshold level of thermal conductivity is achieved at a cryogenic temperature range in which a quantum circuit operates. In an embodiment, the device also includes a second substrate disposed in a recess of the first substrate, the second substrate formed of a second material that exhibits a second threshold level of thermal conductivity. The second threshold level of thermal conductivity is achieved at a cryogenic temperature range in which a quantum circuit operates. In an embodiment, at least one qubit is disposed on the second substrate. In an embodiment, the device also includes a transmission line configured to carry a microwave signal between the first substrate and the second substrate.

The subject disclosure is directed towards layered substrate structures with aligned optical access to electrical devices formed thereon for laser processing and electrical device tuning. According to an embodiment, a layered substrate structure is provided that comprises an optical substrate having a first surface and a second surface and a patterned bonding layer formed on the second surface that comprises a bonding region and an open region, wherein the open region exposes a portion of the second surface. The layered substrate structure further comprises a device chip bonded to the patterned bonding layer via the bonding region and comprising at least one electrical component aligned with the optical substrate and the open region. The at least one electrical component can include for example, a thin film wire, an air bridge, a qubit, an electrode, a capacitor or a resonator.