A semiconductor structure includes a substrate, at least one first gate structure, at least one source drain structure, at least one bottom conductor, and a first dielectric layer. The first gate structure is present on the substrate. The source drain structure is present on the substrate. The bottom conductor is electrically connected to the source drain structure. The bottom conductor has an upper portion and a lower portion between the upper portion and the source drain structure, and a gap is at least present between the upper portion of the bottom conductor and the first gate structure. The first dielectric layer is at least present between the lower portion of the bottom conductor and the first gate structure.

A semiconductor structure includes a substrate, at least one first gate structure, at least one source drain structure, at least one bottom conductor, and a first dielectric layer. The first gate structure is present on the substrate. The source drain structure is present on the substrate. The bottom conductor is electrically connected to the source drain structure. The bottom conductor has an upper portion and a lower portion between the upper portion and the source drain structure, and a gap is at least present between the upper portion of the bottom conductor and the first gate structure. The first dielectric layer is at least present between the lower portion of the bottom conductor and the first gate structure.

A semiconductor device that includes a gate structure on a channel region of a semiconductor device. Source and drain regions may be present on opposing sides of the channel region. The semiconductor device may further include a composite gate sidewall spacer present on a sidewall of the gate structure. The composite gate sidewall spacer may include a first composition portion having an air gap encapsulated therein, and a second composition portion that is entirely solid and present atop the first composition portion.

A semiconductor device that includes a gate structure on a channel region of a semiconductor device. Source and drain regions may be present on opposing sides of the channel region. The semiconductor device may further include a composite gate sidewall spacer present on a sidewall of the gate structure. The composite gate sidewall spacer may include a first composition portion having an air gap encapsulated therein, and a second composition portion that is entirely solid and present atop the first composition portion.

A method for forming a semiconductor device. In this method, a semiconductor fin is formed on a semiconductor substrate. Two cells adjacent to each other are formed on the semiconductor fin. A gate conductor is formed on a top of the semiconductor fin at a common boundary that is shared by the two cells. A gate spacer is formed to peripherally enclose the gate conductor. The gate conductor and the semiconductor fin are etched to form an air gap, thereby dividing the semiconductor fin into two portions of the semiconductor fin. A dielectric cap layer is deposited into the air gap to cap a top of the air gap.

A memory device includes a semiconductor substrate, an isolation layer disposed on the semiconductor substrate, a first conductive layer disposed on the isolation layer, at least one contact plug passing through the isolation layer and electrically contacting the semiconductor substrate with the first conductive layer, a plurality of insulating layers disposed on the first conductive layer, a plurality of second conductive layers alternatively stacked with the insulating layers and insulated from the first conductive layer, a channel layer disposed on at least one sidewall of a first through opening and electrically contacting to the contact plug, wherein the first through opening passes through the insulating layers and the second conductive layers to expose the contact plug, and a memory layer disposed between the channel layer and the second conductive layers.

The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate having an active region and an isolation region. The semiconductor structure includes gate stacks on the substrate that extend over the active region and the isolation region. The semiconductor structure includes a gate spacer on sidewalls of the gate stacks. The semiconductor structure includes an interlevel dielectric (ILD) layer over the substrate and implanted with one or more dopants, the ILD layer having a top implanted portion over a bottom nonimplanted portion. The top implanted portion seals an air gap between a sidewall of the ILD layer and the gate spacer.

Techniques are provided herein to form an integrated circuit having dielectric material formed in cavities beneath source or drain regions. The cavities may be formed within subfin portions of semiconductor devices. In one such example, a FET (field effect transistor) includes a gate structure extending around a fin or any number of nanowires of semiconductor material. The semiconductor material may extend in a first direction between source and drain regions while the gate structure extends over the semiconductor material in a second direction substantially orthogonal to the first direction. A dielectric fill may be formed in a recess beneath the source or drain regions, or a dielectric liner may be formed on sidewalls of the recess, to prevent epitaxial growth of the source or drain regions from the subfins. Removal of the semiconductor subfin from the backside may then be performed without causing damage to the source or drain regions.

A method of manufacturing a semiconductor device includes forming a cured portion by heating a semiconductor substrate in a non-oxidizing atmosphere to cure a front surface of a first insulation material that was not removed in a first-etching and remains in a deep side of the trench; forming a cavity in the trench on a deeper side of the cured portion by making an etchant enter into the trench from an interface to the deeper side to perform a second-etching and removing the first insulation material remaining in the deeper side of the cured portion, the interface being present between portions of the first insulation material that have been grown from side surfaces of the trench, wherein an opening is formed at the interface by the second-etching; and closing the opening at the interface with a second insulation material.

A memory device includes a semiconductor substrate, an isolation layer disposed on the semiconductor substrate, a first conductive layer disposed on the isolation layer, at least one contact plug passing through the isolation layer and electrically contacting the semiconductor substrate with the first conductive layer, a plurality of insulating layers disposed on the first conductive layer, a plurality of second conductive layers alternatively stacked with the insulating layers and insulated from the first conductive layer, a channel layer disposed on at least one sidewall of a first through opening and electrically contacting to the contact plug, wherein the first through opening passes through the insulating layers and the second conductive layers to expose the contact plug, and a memory layer disposed between the channel layer and the second conductive layers.