A method for defining a length of a fin including forming a plurality of first slice walls on a mask material layer, which is provided over the fin, using a plurality of hard mask patterns, providing a plurality of fill mask patterns self-aligned with respect to the plurality of first slice walls to expose one or more select areas between one or more pairs of adjacent ones of the plurality of first slice walls, and providing a trim mask pattern including one or more openings and self-aligned with respect to the plurality of second slice walls to expose one or more of the plurality of first slice walls may be provided.

In an HEMT device, a gate region is formed in a wafer having a channel layer, a barrier layer, and a passivation layer, overlying each other. Drain and source electrodes are formed in the wafer, on different sides of the gate region. A dielectric layer is formed over the gate region and over the passivation layer. Selective portions of the dielectric layer are removed by a plurality of etches so as to form one or more cavities between the gate region and the drain electrode. The one or more cavities have a plurality of steps at an increasing distance from the wafer moving from the gate region to the drain electrode. The cavity is then filled with conductive material to form a field plate coupled to the source electrode, extending over the gate region, and having a surface facing the wafer and having a plurality of steps.

According to one embodiment, a semiconductor device includes a first electrode, a semiconductor layer, and a first insulating portion. The first electrode includes first and second electrode regions. The semiconductor layer includes first to third semiconductor regions, and third and fourth partial regions. The first semiconductor region includes first and second partial regions. The first partial region is separated from the first electrode region. The second semiconductor region is separated from the second partial region. The third semiconductor region is provided between the second partial region and the second semiconductor region. The third partial region is separated from the second electrode region. The fourth partial region is separated from the second electrode region. The first insulating portion is provided between the electrode region and the partial region and between the electrode region and the semiconductor region. The first insulating portion has a first width and a second width.

A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.

A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.

Proton irradiation is performed a plurality of times from rear surface of an n-type semiconductor substrate, which is an n.sup. drift layer, forming an n-type FS layer having lower resistance than the n-type semiconductor substrate in the rear surface of the n.sup. drift layer. When the proton irradiation is performed a plurality of times, the next proton irradiation is performed to as to compensate for a reduction in mobility due to disorder which remains after the previous proton irradiation. In this case, the second or subsequent proton irradiation is performed at the position of the disorder which is formed by the previous proton irradiation. In this way, even after proton irradiation and a heat treatment, the disorder is reduced and it is possible to prevent deterioration of characteristics, such as increase in leakage current. It is possible to form an n-type FS layer including a high-concentration hydrogen-related donor layer.

Fabrication methods and device structures for bipolar junction transistors and heterojunction bipolar transistors. A first dielectric layer is formed and a second dielectric layer is formed on the first dielectric layer. An opening is etched extending vertically through the first dielectric layer and the second dielectric layer. A collector is formed inside the opening. An intrinsic base, which is also formed inside the opening, has a vertical arrangement relative to the collector.

Device structures and fabrication methods for a heterojunction bipolar transistor. A collector of the device structure has a top surface and a sidewall that is inclined relative to the top surface. The device structure further includes an emitter, an intrinsic base that has a first thickness, and an extrinsic base coupled with the intrinsic base. The extrinsic base has a lateral arrangement relative to the intrinsic base and relative to the emitter. The intrinsic base has a vertical arrangement between the emitter and the top surface of the collector. The sidewall of the collector extends laterally to undercut the extrinsic base. The extrinsic base has a second thickness that is greater than a first thickness of the intrinsic base.

In one general aspect, a method of fabricating a power device can include preparing a semiconductor substrate of a first conductivity type, and forming a first Field Stop (FS) layer and a second FS layer.

Embodiments are directed to a method and resulting structures for smoothing the sidewall roughness of a post-etched film. A sacrificial layer is formed on a substrate. A patterned mask is formed by removing portions of the sacrificial layer to expose a surface of the substrate. The sidewalls of the patterned mask are smoothed and a target layer is formed over the patterned mask and the substrate. Portions of the target layer are removed to expose a surface of the patterned mask and the patterned mask is removed.