Patent classifications
H01L21/36
Apparatus and methods for annealing wafers
A method includes performing an anneal on a wafer. The wafer includes a wafer-edge region, and an inner region encircled by the wafer-edge region. During the anneal, a first power applied on a portion of the wafer-edge region is at least lower than a second power for annealing the inner region.
Method for producing a graphene-based sensor
In accordance with an embodiment, a method for producing a graphene-based sensor includes providing a carrier substrate; forming a carrier structure on the carrier substrate, wherein one or more separating structures are formed on an upper side of the carrier structure; and performing a wet chemical transfer of a graphene layer onto the upper side of the carrier structure that comprises the separating structures, where the separating structures and a tear strength of the graphene layer are matched to one another such that the graphene layer respectively tears at the separating structures during the wet chemical transfer.
Gapfill using reactive anneal
Methods for seam-less gapfill comprising forming a flowable film by PECVD, annealing the flowable film with a reactive anneal to form an annealed film and curing the flowable film or annealed film to solidify the film. The flowable film can be formed using a higher order silane and plasma. The reactive anneal may use a silane or higher order silane. A UV cure, or other cure, can be used to solidify the flowable film or the annealed film.
Methods for forming low temperature semiconductor layers and related semiconductor device structures
A method for forming a metal nitride film with good film closure at low temperatures is disclosed. The method may comprise utilizing plasma to form NH and NH.sub.2 radicals to allow for the formation of the metal nitride at low temperatures. The method may also comprise flowing an etch gas to result in an amorphous film with uniform thickness. The method may also comprise flowing an alkyl hydrazine to inhibit three-dimensional island growth of the metal nitride film.
Multi-layer silicon/gallium nitride semiconductor
The electrical and electrochemical properties of various semiconductors may limit the usefulness of various semiconductor materials for one or more purposes. A completed gallium nitride (GaN) semiconductor layer containing a number of GaN power management integrated circuit (PMIC) dies may be bonded to a completed silicon semiconductor layer containing a number of complementary metal oxide (CMOS) control circuit dies. The completed GaN layer and the completed silicon layer may be full size (e.g., 300 mm). A layer transfer operation may be used to bond the completed GaN layer to the completed silicon layer. The layer transfer operation may be performed on full size wafers. After slicing the full size wafers a large number of multi-layer dies, each having a GaN die layer transferred to a silicon die may be produced.
Laser annealing apparatus and laser annealing method for substrate
A laser annealing apparatus including a carrying platform with a fixing surface, a laser source and a driving device. The laser source is configured to emit a laser beam toward the fixing surface, the laser beam having an illumination area which covers a center of the fixing surface and extends toward an edge of the fixing surface, in an extending direction of the illumination area the illumination area having a length which is not less than a distance between the center of the fixing surface and the edge of the fixing surface. The driving device is configured to drive the carrying platform to rotate around the center of the fixing surface.
Flexible display device
A flexible display device includes: a flexible substrate; a thin-film transistor on the flexible substrate; a passivation film covering the thin-film transistor; and a display element on the passivation film and electrically connected to the thin-film transistor. The passivation film includes a material exhibiting a shear-thickening phenomenon.
Multi-color monolithic light-emitting diodes and methods for making the same
A process for producing a light emitting diode device, the process including: forming a plurality of quantum dots on a surface of a layer including a first area and a second area, the forming including: exposing the first area of the surface to light having a first wavelength while exposing the first area to a quantum dot forming environment that causes the quantum dots in the first area to form at a first growth rate while the quantum dots have a dimension less than a first threshold dimension; exposing the second area of the surface to light having a second wavelength while exposing the second area to the quantum dot forming environment that causes the quantum dots in the second area to form at a third growth rate while the quantum dots have a dimension less than a second threshold dimension; and processing the layer to form the LED device.
High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed on a substrate with a rough surface
A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and the front surface of the single crystal semiconductor handle substrate has a surface roughness of at least about 0.1 micrometers as measured according to the root mean square method over a surface area of at least 30 micrometers by 30 micrometers. The composite structure further comprises a charge trapping layer in contact with the front surface, the charge trapping layer comprising poly crystalline silicon, the poly crystalline silicon comprising grains having a plurality of crystal orientations; a dielectric layer in contact with the charge trapping layer; and a single crystal semiconductor device layer in contact with the dielectric layer.
Method and apparatus for back-biased switch transistors
An integrated radio frequency (RF) circuit structure may include an active device on a first surface of an isolation layer. The integrated RF circuit structure may also include a back-bias metallization on a second surface opposite the first surface of the isolation layer. A body of the active device is biased by the back-bias metallization. The integrated RF circuit structure may further include a handle substrate on a front-side dielectric layer on the active device.