To provide a miniaturized transistor having highly stable electrical characteristics. Furthermore, also in a semiconductor device including the transistor, high performance and high reliability are achieved. The transistor includes, over a substrate, a conductor, an oxide semiconductor, and an insulator. The oxide semiconductor includes a first region and a second region. The resistance of the second region is lower than that of the first region. The entire surface of the first region in the oxide semiconductor is surrounded in all directions by the conductor with the insulator interposed therebetween.

Use of a single alloy conductor to form simultaneous ohmic contacts (SOC) to n- and p-type 4H-SiC. The single alloy conductor also is an effective diffusion barrier against gold (AU) and oxygen (O.sub.2) at high temperatures (e.g., up to 800 C.). The innovation may also provide an effective interconnecting metallization in a multi-level metallization device scheme.

A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. A topmost location of the epitaxy structure has an n-type impurity concentration lower than an n-type impurity concentration of a location of the epitaxy structure below the topmost location.

Disclosed are a semiconductor device and a manufacturing method thereof. According to the semiconductor device and the manufacturing method thereof according to exemplary embodiments of the present invention, after the dopant source layer is uniformly deposited on a channel layer of the device with the 3-dimensional vertical structure by the plasma-enhanced atomic layer deposition (PEALD) method, the deposited dopant source layer is heat-treated so that the dopants are diffused into the channel layer to function as charge carriers, thereby preventing the charges in the channel layer from being reduced. According to the exemplary embodiments of the present invention, the diffusion speed and concentration of the dopant may be controlled by forming the barrier layer between the channel layer and the dopant source layer.

Disclosed is a method for manufacturing a semiconductor device, which includes providing a template having a first substrate and a patterned first III-V group compound layer located on the first substrate, forming a sacrificial layer on the patterned first III-V group compound layer by epitaxial growth, forming a second III-V group compound layer on the sacrificial layer by epitaxial growth, bonding a second substrate made of silicon onto the second III-V group compound layer, and separating the second III-V group compound layer and the second substrate from the template by removing the sacrificial layer.

A super junction includes a substrate and an epitaxial layer over the substrate, the epitaxial layer having a first dopant type. The super junction further includes an angled trench in the epitaxial layer, the angled trench having sidewalls disposed at an angle ranging from about 85-degrees to about 89-degrees with respect to a top surface of the epitaxial layer. The super junction further includes a doped body in the epitaxial layer surrounding the angled trench, the doped body having a second dopant type, the second dopant type opposite that of the first dopant type.

This method for treating a surface of a SiC substrate includes a first removal step in which a modified layer produced by subjecting the substrate (70) to mechanical polishing or chemical-mechanical polishing is removed by heating the substrate (70) under Si vapor pressure. A second removal step in which macro-step bunching occurred in an epitaxial layer (71) is removed by heating the substrate (70) under Si vapor pressure may also be performed. Since the etching rate can be varied, etching rate in the first removal step is high, so that the modified layer can be removed in a short time. Meanwhile, etching rate in the second removal step is comparatively low, so that excessive removal of the epitaxial layer (71) can be prevented.

Layers of high quality VO.sub.2 and methods of fabricating the layers of VO.sub.2 are provided. The layers are composed of a plurality of connected crystalline VO.sub.2 domains having the same crystal structure and the same epitaxial orientation.

Embodiments described herein relate to apparatus and methods of thermal processing. More specifically, apparatus and methods described herein relate to laser thermal treatment of semiconductor substrates by increasing the uniformity of energy distribution in an image at a surface of a substrate.

Novel integrated circuits (SOI ICs), and methods for making and mounting the ICs are disclosed. In one embodiment, an IC comprises a first circuit layer of the IC formed from an active layer of an SOI wafer. The first circuit layer is coupled to a first surface of buffer layer, and a second surface of the buffer layer is coupled to a selected substrate comprising an insulating material. The selected substrate may be selected, without limitation, from the following types: sapphire, quartz, silicon dioxide glass, piezoelectric materials, and ceramics. A second circuit layer of the IC are formed, coupled to a second surface of the selected substrate. In one embodiment of a mounted IC, the first circuit layer is coupled to contact pads on a package substrate via solder bumps or copper pillars. The second circuit layer is coupled to contact pads on the package substrate via wire bonds.