An example standard cell includes: a first active region and a second active region; a first gate strip, where the first gate strip extends in a first direction and is located away from a substrate; two second gate strips, where the first gate strip is located between the two second gate strips, and two ends of the second active region are located close to the substrate; and two spacing regions and two first shallow trench isolation regions, where the first active region is located between the two spacing regions, the second active region is located between the two first shallow trench isolation regions, and a width of each of the two spacing regions and a width of each of the two first shallow trench isolation regions are equal to an arrangement spacing between the first gate strip and the two second gate strips.

A semiconductor device is provided. The semiconductor device includes: first, second and third active patterns on a logic cell region of a substrate and are spaced apart from each other in a first direction; first and second gate electrodes, the first gate electrode crossing the first active pattern and the second gate electrode crossing the second active pattern; a first separation pattern provided between the first and second active patterns; a second separation pattern provided between the second and third active patterns; a first gate insulating layer interposed between the first gate electrode and the first active pattern; and a first gate cutting pattern interposed between the first and second gate electrodes, and in contact with a top surface of the first separation pattern. The first separation pattern is wider than the second separation pattern, and the first gate insulating layer extends between the first gate electrode and the first separation pattern, and contacts side and top surfaces of the first separation pattern.

The invention provides a semiconductor structure, which comprises a first standard cell and a second standard cell located on a substrate, wherein an isolation region is included between the first standard cell and the second standard cell, a plurality of fin structures and a plurality of gates form a plurality of transistors, which are respectively located in the first standard cell and the second standard cell, and a plurality of single diffusion breaks (SDBs) located in the first standard cell and the second standard cell. A plurality of first dummy grooves in the first standard cell and the second standard cell, and a plurality of second dummy grooves in the isolation region, wherein some of the second dummy grooves overlap the first dummy grooves.

A semiconductor device includes a substrate including an N-stack cell, a buffer cell and an M-stack cell that are on the substrate, the buffer cell being between the N-stack and M-stack cells, an active pattern extending from the N-stack cell to the M-stack cell via the buffer cell, an N-stack channel pattern on the active pattern of the N-stack cell, an M-stack channel pattern on the active pattern of the M-stack cell, a dummy channel pattern on the active pattern of the buffer cell, an N-stack epitaxial pattern between the N-stack channel pattern and the dummy channel pattern, and an M-stack epitaxial pattern between the M-stack channel pattern and the dummy channel pattern. The N-stack channel pattern includes stacked N semiconductor patterns. The M-stack channel pattern includes stacked M semiconductor patterns. Each of N and M is an integer number of 2 or more, and M is greater than N.

A semiconductor device includes a plurality of semiconductor elements, each of the plurality of semiconductor elements including an active region disposed on a substrate, and a gate structure intersecting the active region and extending in a first direction that is parallel to an upper surface of the substrate; and at least one dummy element disposed between a pair of semiconductor elements adjacent to each other in a second direction, intersecting the first direction, among the plurality of semiconductor elements. The dummy element includes a dummy active region and at least one dummy gate structure intersecting the dummy active region and extending in the first direction. A length of the dummy active region in the second direction is less than a length of the active region included in each of the pair of semiconductor elements.

A semiconductor device includes: a first gate structure at least partially overlapping first and second active regions; second and third gate structures at least partially overlapping the first active region; fourth and fifth gate structures at least partially overlapping the second active region; a first conductive structure between the first and third gate structures and in contact with the first active region; a first electrical connection connecting the first gate structure with the first conductive structure; a second conductive structure between the first and fifth gate structures and in contact with the second active region; a second electrical connection connecting the first gate structure with the second conductive structure; a third electrical connection connecting the second gate structure with the third gate structure and the first conductive structure; and a fourth electrical connection connecting the fourth gate structure with the fifth gate structure and the second conductive structure.

An integrated circuit includes a first transistor of a first type, a floating gate transistor, a second transistor of a second type, and a first and second conductor. The floating gate transistor includes a drain and a source coupled to a first voltage supply, and a floating gate located on a first level, and being electrically floating. The second transistor includes a first gate separated from the floating gate in a first direction. The first conductor is on a second level, overlaps the floating gate, and is not electrically coupled to the floating gate. The second conductor is on the second level, overlaps the first gate, is separated from the first conductor in the second direction, and is electrically coupled to the second transistor.

The invention provides a semiconductor structure, which comprises a first standard cell and a second standard cell located on a substrate, wherein an isolation region is included between the first standard cell and the second standard cell, and a boundary of the first standard cell aligns with a boundary of the isolation region, a plurality of fin structures and a plurality of gates form a plurality of transistors, which are respectively located in the first standard cell and the second standard cell, and a plurality of single diffusion breaks (SDBs) located in the first standard cell and the second standard cell. A plurality of first dummy grooves in the first standard cell and the second standard cell, and a plurality of second dummy grooves in the isolation region, wherein some of the second dummy grooves overlap the first dummy grooves.

The invention provides a semiconductor structure, which comprises a first standard cell and a second standard cell located on a substrate, wherein an isolation region is included between the first standard cell and the second standard cell, a plurality of fin structures and a plurality of gates form a plurality of transistors, which are respectively located in the first standard cell and the second standard cell, and a plurality of single diffusion breaks (SDBs) located in the first standard cell and the second standard cell. A plurality of first dummy grooves in the first standard cell and the second standard cell, and a plurality of second dummy grooves in the isolation region, wherein some of the second dummy grooves overlap the first dummy grooves.

An embodiment semiconductor structure includes a first active region and a second active region extending along a first direction, a functional gate structure and a non-functional gate structure aligned with each other and extending along a second direction, and a metallization layer over the functional gate structure and the non-functional gate structure. The metallization layer defines a first metallization region, a second metallization region, and one or two middle metallization regions between the first metallization region and the second metallization region. The functional gate structure overlaps the first metallization region and overlaps one of the one or two middle metallization regions to define an overlapped portion of the one of the one or two middle metallization regions. The overlapped portion has a space defined therein sized for a connection feature between the functional gate structure and the one of the one or two middle metallization regions.